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Clock Domain Crossing MCQs

Practice Clock Domain Crossing MCQs with four options, answers and explanations for focused Electronics & Telecommunication Engineering revision.

Question 1
Digital ElectronicsClock Domain Crossing

Why is a two-flip-flop synchronizer commonly used when a single-bit asynchronous signal enters a synchronous clock domain?

  • ATo reduce the probability that metastability propagates into downstream logic
  • BTo double the asynchronous signal frequency
  • CTo convert binary to BCD
  • DTo remove the clock
Report an error
Correct Answer: A. To reduce the probability that metastability propagates into downstream logic
Explanation: The first flip-flop may become metastable, while the second provides additional resolution time before the signal is used by downstream synchronous logic, greatly reducing failure probability.
Reference: Standard digital electronics: asynchronous input synchronization