ADC & DAC MCQs

Practice ADC & DAC MCQs with four options, answers and explanations for focused Electronics & Telecommunication Engineering revision.

Question 1

Digital ElectronicsADC & DAC

An ADC performs which conversion?

ADigital to analog
BAnalog to digital
CFrequency to resistance only
DBinary to decimal display only

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Correct Answer: B. Analog to digital

Explanation: An analog-to-digital converter converts an analog input quantity into a digital representation.

Reference: Standard digital electronics: ADC

Question 2

Digital ElectronicsADC & DAC

A DAC performs which conversion?

AAnalog to digital
BDigital to analog
CAC to DC power conversion
DSerial to parallel only

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Correct Answer: B. Digital to analog

Explanation: A digital-to-analog converter converts a digital code into a corresponding analog output.

Reference: Standard digital electronics: DAC

Question 3

Digital ElectronicsADC & DAC

An ideal 8-bit ADC provides how many quantization levels?

A8
B16
C128
D256

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Correct Answer: D. 256

Explanation: An ideal n-bit ADC has 2^n quantization levels. For 8 bits, this is 256 levels.

Reference: Standard digital electronics: ADC resolution

Question 4

Digital ElectronicsADC & DAC

Increasing the number of bits of an ideal ADC generally?

AReduces the number of available codes
BImproves resolution
CEliminates the need for sampling
DMakes the output analog

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Correct Answer: B. Improves resolution

Explanation: More bits provide more quantization levels, allowing smaller input changes to be represented and therefore improving resolution.

Reference: Standard digital electronics: ADC resolution

Question 5

Digital ElectronicsADC & DAC

An ideal 10-bit ADC has an input range of 0 to 5.12 V. Using 2^N quantization levels, the nominal voltage represented by one LSB is?

A0.5 mV
B5 mV
C10 mV
D50 mV

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Correct Answer: B. 5 mV

Explanation: A 10-bit ADC has 1024 levels. 5.12 V / 1024 = 0.005 V = 5 mV per LSB under this convention.

Reference: Standard digital electronics: ideal ADC resolution

Question 6

Digital ElectronicsADC & DAC

For an ideal 8-bit DAC with a 5.12 V full-scale range interpreted over 256 equal steps, one LSB corresponds to?

A2 mV
B10 mV
C20 mV
D50 mV

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Correct Answer: C. 20 mV

Explanation: Using 2^8 = 256 equal steps, 5.12 V / 256 = 0.02 V = 20 mV per LSB.

Reference: Standard digital electronics: ideal DAC resolution

Question 7

Digital ElectronicsADC & DAC

Which ADC architecture is generally known for very high conversion speed because it uses many comparators in parallel?

ADual-slope ADC
BFlash ADC
CSuccessive-approximation ADC
DIntegrating ADC only

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Correct Answer: B. Flash ADC

Explanation: A flash ADC compares the input simultaneously against many reference levels, providing very fast conversion at the cost of many comparators.

Reference: Standard digital electronics: ADC architectures

Question 8

Digital ElectronicsADC & DAC

A successive-approximation ADC determines the digital output primarily by?

ATesting bits through a binary-search-like sequence
BCounting indefinitely until power is removed
CUsing only one fixed comparator threshold with no DAC
DDirectly storing the analog voltage as binary charge

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Correct Answer: A. Testing bits through a binary-search-like sequence

Explanation: A SAR ADC successively tests candidate bits, effectively performing a binary search using an internal DAC and comparator.

Reference: Standard digital electronics: SAR ADC

Question 9

Digital ElectronicsADC & DAC

Ignoring overhead, an ideal 12-bit successive-approximation ADC that performs one bit decision per clock requires approximately how many comparison steps for one conversion?

A6
B10
C12
D4096

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Correct Answer: C. 12

Explanation: A SAR converter determines one output bit per successive approximation step, so an ideal 12-bit conversion requires about 12 bit decisions.

Reference: Standard digital electronics: SAR conversion

Question 10

Digital ElectronicsADC & DAC

An n-bit flash ADC requires approximately how many comparators for direct quantization into 2^n levels?

An
B2n
C2^n - 1
D2^n + 1

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Correct Answer: C. 2^n - 1

Explanation: A conventional n-bit flash ADC uses one comparator for each decision threshold between adjacent output levels, giving 2^n − 1 comparators.

Reference: Standard digital electronics: flash ADC comparator count

Question 11

Digital ElectronicsADC & DAC

How many comparators are required in a conventional 8-bit flash ADC?

A8
B127
C255
D256

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Correct Answer: C. 255

Explanation: For n=8, the flash ADC comparator count is 2^8 − 1 = 255.

Reference: Standard digital electronics: flash ADC comparator count

Question 12

Digital ElectronicsADC & DAC

For an ideal R-2R ladder DAC, one major practical advantage over a binary-weighted-resistor DAC is that the ladder requires?

AOnly two resistor values
BNo resistors
CA different resistor for every possible code
DOnly capacitors

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Correct Answer: A. Only two resistor values

Explanation: An R-2R ladder is constructed using only R and 2R values, simplifying resistor matching and IC implementation compared with a wide range of binary-weighted resistor values.

Reference: Standard digital electronics: R-2R DAC

Question 13

Digital ElectronicsADC & DAC

For an ideal 4-bit unipolar DAC whose output magnitude is proportional to unsigned input code, which input code produces the largest output?

A0000
B0111
C1000
D1111

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Correct Answer: D. 1111

Explanation: For an unsigned 4-bit DAC, code value increases from 0000 to the maximum code 1111, so 1111 produces the largest ideal output.

Reference: Standard digital electronics: DAC codes

Question 14

Digital ElectronicsADC & DAC

A sample-and-hold circuit placed ahead of an ADC is primarily used to?

AKeep the analog input approximately constant during conversion
BGenerate the ADC clock
CStore the final digital code permanently
DIncrease the number of ADC bits automatically

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Correct Answer: A. Keep the analog input approximately constant during conversion

Explanation: The sample-and-hold captures the instantaneous analog input and holds it nearly constant so the ADC sees a stable value while conversion is in progress.

Reference: Standard digital electronics: sample-and-hold

Question 15

Digital ElectronicsADC & DAC

An ideal 10-bit ADC has an input range from 0 to 5.12 V divided into 1024 equal code steps. The nominal voltage represented by one LSB is?

A0.5 mV
B5 mV
C10 mV
D20 mV

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Correct Answer: B. 5 mV

Explanation: An ideal 10-bit converter has 2^10=1024 steps. Thus one LSB = 5.12 V/1024 = 0.005 V = 5 mV.

Reference: Standard digital electronics: ADC resolution

Question 16

Digital ElectronicsADC & DAC

A dual-slope ADC is particularly valued in digital measurement instruments because its integrating operation provides good rejection of?

ACertain periodic noise such as mains-frequency interference
BAll possible quantization error
CEvery clock error regardless of frequency
DMemory leakage

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Correct Answer: A. Certain periodic noise such as mains-frequency interference

Explanation: Dual-slope conversion integrates the input over a defined interval; choosing the interval appropriately can strongly reject periodic interference such as 50/60 Hz mains noise.

Reference: Standard digital electronics: dual-slope ADC

Question 17

Digital ElectronicsADC & DAC

In an ADC, differential nonlinearity (DNL) describes deviation of?

AAn individual code-bin width from the ideal 1-LSB step
BThe supply voltage from zero
CThe clock duty cycle from 100 percent
DThe number of output bits from an integer

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Correct Answer: A. An individual code-bin width from the ideal 1-LSB step

Explanation: DNL measures how much each actual transition step or code-bin width differs from the ideal one-LSB size.

Reference: Standard digital electronics: ADC differential nonlinearity

Question 18

Digital ElectronicsADC & DAC

An ADC is said to have a missing code when?

AAt least one digital output code is never produced for any input within the conversion range
BEvery code occurs twice
CThe input is exactly zero
DThe ADC has no clock pin

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Correct Answer: A. At least one digital output code is never produced for any input within the conversion range

Explanation: A missing code is an output value that the converter skips entirely as the analog input is swept through its range, often associated with excessive DNL.

Reference: Standard digital electronics: ADC missing codes

Question 19

Digital ElectronicsADC & DAC

For an ideal monotonic DAC, increasing the digital input code by one count should?

ANever cause the analog output to move in the opposite direction
BAlways force the output to zero
CReverse the output polarity every step
DProduce exactly two output transitions

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Correct Answer: A. Never cause the analog output to move in the opposite direction

Explanation: Monotonicity means the analog output never reverses direction when the input code changes monotonically in one direction.

Reference: Standard digital electronics: DAC monotonicity

Question 20

Digital ElectronicsADC & DAC

A DAC has a settling time specification of 2 microseconds. This specification primarily indicates the time required after an input-code change for the analog output to?

AEnter and remain within a specified error band around its final value
BBegin oscillating indefinitely
CBecome a digital code
DErase the input register

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Correct Answer: A. Enter and remain within a specified error band around its final value

Explanation: Settling time is measured from a code transition until the analog output reaches and stays within a specified tolerance around its final value.

Reference: Standard digital electronics: DAC settling time