Memory MCQs

Explanation: EEPROM stands for electrically erasable programmable read-only memory and can be erased and programmed electrically.

Explanation: RAM is volatile because its stored data is normally lost when power is removed.

Explanation: ROM is non-volatile and retains its stored information without operating power.

Explanation: SRAM uses bistable circuitry for each stored bit and does not require periodic refresh while powered.

Explanation: DRAM cells store information as electrical charge on capacitors, and leakage requires periodic refreshing.

Explanation: Capacity = number of locations × bits per location = 1024 × 8 = 8192 bits.

Explanation: 4096 = 2^12, so 12 binary address lines are needed.

Explanation: 8K means 8 × 1024 = 8192 addressable words, with 16 bits stored in each word.

Explanation: 8K = 8192 = 2^13 locations, so 13 address lines are required.

Explanation: There are 4096 words of 8 bits each, giving 4096 × 8 = 32768 bits = 32 Kbits.

Explanation: The organization 2K × 16 means 2048 addressable words, each 16 bits wide. Therefore 16 data lines are required for a parallel word transfer.

Explanation: Selecting one of four chips requires log2(4)=2 selection bits. The lower 10 address bits address locations within each 1K chip.

Explanation: A DRAM cell stores data as capacitor charge that leaks with time, so rows must be periodically refreshed.

Explanation: SRAM uses bistable circuitry and normally offers faster access without refresh, although it uses more devices per bit and has lower density than DRAM.

Explanation: EEPROM is electrically erasable and programmable. Traditional EPROM requires ultraviolet light for erasure, while EEPROM supports electrical rewriting.

Explanation: Flash memory is generally organized so erase operations affect blocks or sectors, enabling higher density than conventional byte-oriented EEPROM implementations.

Explanation: Dual-port memory provides two access interfaces, enabling two agents or datapaths to access a shared memory array with suitable arbitration or port rules.

Explanation: FIFO means First-In, First-Out: entries leave the buffer in the same order in which they entered.

Explanation: FIFO control logic tracks read and write positions and derives EMPTY and FULL conditions to prevent invalid reads and overwriting of unread data.