Timing & Clock MCQs

Practice Timing & Clock MCQs with four options, answers and explanations for focused Electronics & Telecommunication Engineering revision.

Question 1

Digital ElectronicsTiming & Clock

Propagation delay of a digital gate is the time between?

AApplying power and permanently damaging the gate
BAn input transition and the corresponding output transition
CTwo unrelated clock cycles only
DWriting and erasing ROM

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Correct Answer: B. An input transition and the corresponding output transition

Explanation: Propagation delay is the finite time from a relevant change at a gate input to the resulting change at its output.

Reference: Standard digital electronics: propagation delay

Question 2

Digital ElectronicsTiming & Clock

A T flip-flop is driven by a 1 MHz clock and toggles on every active clock edge. Its output frequency is?

A2 MHz
B1 MHz
C500 kHz
D250 kHz

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Correct Answer: C. 500 kHz

Explanation: A toggling flip-flop changes state once per clock edge and completes one output cycle in two clock periods, dividing frequency by 2.

Reference: Standard digital electronics: frequency division

Question 3

Digital ElectronicsTiming & Clock

A 4-bit ripple counter uses flip-flops having 20 ns propagation delay each. Approximately what worst-case ripple settling delay can occur through all four stages?

A20 ns
B40 ns
C80 ns
D160 ns

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Correct Answer: C. 80 ns

Explanation: For a simple ripple counter, worst-case delay approximately accumulates across stages: 4 × 20 ns = 80 ns.

Reference: Standard digital electronics: ripple counter propagation delay

Question 4

Digital ElectronicsTiming & Clock

For an edge-triggered D flip-flop, the input D must remain stable for specified intervals immediately before and after the active clock edge. These intervals are called?

ARise time and fall time
BSetup time and hold time
CPropagation time and recovery time
DAccess time and cycle time

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Correct Answer: B. Setup time and hold time

Explanation: Setup time is the minimum interval D must be stable before the active clock edge, while hold time is the minimum interval it must remain stable afterward.

Reference: Standard digital electronics: flip-flop timing

Question 5

Digital ElectronicsTiming & Clock

If a flip-flop’s setup or hold time requirement is violated, the device may enter?

ASaturation only
BMetastability
CPermanent tri-state operation
DFrequency multiplication

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Correct Answer: B. Metastability

Explanation: Violating setup or hold requirements can leave a flip-flop temporarily in an indeterminate or metastable state before it resolves to a valid logic level.

Reference: Standard digital electronics: metastability