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MCQ Practice Question
Digital ElectronicsSequential Timing

A synchronous finite-state machine has a maximum combinational-path delay of 18 ns and flip-flop setup time of 2 ns. Ignoring clock skew and clock-to-Q delay, the clock period must be at least?

  • A9 ns
  • B16 ns
  • C18 ns
  • D20 ns
Report an error
Correct Answer: D. 20 ns
Explanation: The receiving flip-flop needs stable data before the clock edge, so Tclk ≥ 18 ns + 2 ns = 20 ns under the stated assumptions.
Reference: Standard digital electronics: synchronous timing
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