Sequential Timing MCQs

Practice Sequential Timing MCQs with four options, answers and explanations for focused Electronics & Telecommunication Engineering revision.

Question 1

Digital ElectronicsSequential Timing

A synchronous finite-state machine has a maximum combinational-path delay of 18 ns and flip-flop setup time of 2 ns. Ignoring clock skew and clock-to-Q delay, the clock period must be at least?

A9 ns
B16 ns
C18 ns
D20 ns

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Correct Answer: D. 20 ns

Explanation: The receiving flip-flop needs stable data before the clock edge, so Tclk ≥ 18 ns + 2 ns = 20 ns under the stated assumptions.

Reference: Standard digital electronics: synchronous timing

Question 2

Digital ElectronicsSequential Timing

Two flip-flops receive the same nominal clock edge at slightly different times because of unequal clock-path delays. This timing difference is called?

AClock skew
BFan-out
CQuantization
DAliasing

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Correct Answer: A. Clock skew

Explanation: Clock skew is the difference in arrival time of the same clock edge at different sequential elements.

Reference: Standard digital electronics: clock skew

Question 3

Digital ElectronicsSequential Timing

A positive-edge-triggered D flip-flop has setup time 3 ns and hold time 1 ns. For reliable operation, the D input must be stable for at least which interval around the active clock edge?

A3 ns before and 1 ns after
B1 ns before and 3 ns after
COnly 3 ns after
DOnly at the exact clock instant

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Correct Answer: A. 3 ns before and 1 ns after

Explanation: Setup time requires data to be stable for 3 ns before the active edge, and hold time requires it to remain stable for 1 ns after the edge.

Reference: Standard digital electronics: setup and hold time

Question 4

Digital ElectronicsSequential Timing

If the setup or hold requirement of a flip-flop is violated, the flip-flop may temporarily enter which condition?

AMetastability
BPermanent tri-state
CFrequency lock
DQuantization

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Correct Answer: A. Metastability

Explanation: A timing violation can leave a bistable element temporarily between valid logic states. This metastable condition eventually resolves, but its resolution time is not precisely predictable.

Reference: Standard digital electronics: metastability

Question 5

Digital ElectronicsSequential Timing

For a register-to-register synchronous path, Tcq=2 ns, maximum combinational delay=11 ns, setup time=2 ns, and worst-case clock uncertainty=1 ns. What minimum clock period is required using Tclk ≥ Tcq + Tcomb + Tsetup + Tuncertainty?

A12 ns
B14 ns
C16 ns
D18 ns

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Correct Answer: C. 16 ns

Explanation: Substituting the values gives Tclk ≥ 2+11+2+1 = 16 ns.

Reference: Standard digital electronics: maximum clock frequency timing

Question 6

Digital ElectronicsSequential Timing

For the synchronous path with a minimum allowed clock period of 16 ns, the corresponding maximum clock frequency is?

A16 MHz
B31.25 MHz
C62.5 MHz
D160 MHz

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Correct Answer: C. 62.5 MHz

Explanation: fmax=1/Tmin=1/(16 ns)=62.5 MHz.

Reference: Standard digital electronics: clock period and frequency

Question 7

Digital ElectronicsSequential Timing

A hold-time check in a synchronous register path is primarily concerned with which path characteristic?

AMinimum or contamination delay
BMaximum combinational delay only
CAverage propagation delay only
DPower-supply frequency

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Correct Answer: A. Minimum or contamination delay

Explanation: Hold analysis checks that new data cannot reach the destination flip-flop too soon after the active clock edge, so minimum path delay is critical.

Reference: Standard digital electronics: hold-time analysis