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Home › Digital Electronics › A positive-edge-triggered D flip-flop has setup time 3 ns and hold time 1 ns. For reliable operation, the D input must be stable for at least which interval around the active clock edge?
MCQ Practice Question
Digital ElectronicsSequential Timing

A positive-edge-triggered D flip-flop has setup time 3 ns and hold time 1 ns. For reliable operation, the D input must be stable for at least which interval around the active clock edge?

  • A3 ns before and 1 ns after
  • B1 ns before and 3 ns after
  • COnly 3 ns after
  • DOnly at the exact clock instant
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Correct Answer: A. 3 ns before and 1 ns after
Explanation: Setup time requires data to be stable for 3 ns before the active edge, and hold time requires it to remain stable for 1 ns after the edge.
Reference: Standard digital electronics: setup and hold time
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