MCQ Practice Question
Why is a two-flip-flop synchronizer commonly used when a single-bit asynchronous signal enters a synchronous clock domain?
Correct Answer: A. To reduce the probability that metastability propagates into downstream logic
Explanation: The first flip-flop may become metastable, while the second provides additional resolution time before the signal is used by downstream synchronous logic, greatly reducing failure probability.
Reference: Standard digital electronics: asynchronous input synchronization