Home › Digital Electronics › For a register-to-register synchronous path, Tcq=2 ns, maximum combinational delay=11 ns, setup time=2 ns, and worst-case clock uncertainty=1 ns. What minimum clock period is required using Tclk ≥ Tcq + Tcomb + Tsetup + Tuncertainty?

MCQ Practice Question

For a register-to-register synchronous path, Tcq=2 ns, maximum combinational delay=11 ns, setup time=2 ns, and worst-case clock uncertainty=1 ns. What minimum clock period is required using Tclk ≥ Tcq + Tcomb + Tsetup + Tuncertainty?

A12 ns
B14 ns
C16 ns
D18 ns

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Correct Answer: C. 16 ns

Explanation: Substituting the values gives Tclk ≥ 2+11+2+1 = 16 ns.

Reference: Standard digital electronics: maximum clock frequency timing

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