DRDO MCQs

Explanation: BW=fH-fL=100000-100=99900 Hz=99.9 kHz.

Explanation: A single pole contributes approximately -20 dB/decade, equivalent to about -6 dB/octave.

Explanation: Each pole contributes about -20 dB/decade, so two coincident poles give approximately -40 dB/decade.

Explanation: Af=A/(1+A beta)=200/(1+4)=40.

Explanation: gm=IC/VT=2 mA/25 mV=0.08 S=80 mS.

Explanation: r_pi=beta/gm=120/0.06=2000 ohm=2 kOhm.

Explanation: For the simplified CE stage, Av≈-gmRC=-0.04×2000=-80.

Explanation: Emitter degeneration introduces local negative feedback, reducing gain but improving linearity and bias stability.

Explanation: The capacitor provides a low-impedance AC path around the emitter resistor while leaving the resistor available for DC bias stabilization.

Explanation: RC coupling transfers the signal while isolating the DC operating points of adjacent amplifier stages.

Explanation: Cascaded voltage gains multiply: 20×15=300.

Explanation: For cascaded stages, gains expressed in decibels add, so total gain is 20+30=50 dB.

Explanation: The cascode suppresses large voltage variation at the input device's output node, reducing Miller effect while retaining useful gain.

Explanation: The desensitivity factor is 1+A beta=1+4=5.

Explanation: Negative feedback commonly trades gain for bandwidth; under the constant gain-bandwidth approximation, a tenfold gain reduction gives about tenfold bandwidth increase.

Explanation: For a non-inverting amplifier, Av=1+Rf/Rg=1+47=48.

Explanation: Av=-Rf/Rin=-4, so Vo=-4×0.5=-2 V.

Explanation: The very large open-loop gain with negative feedback forces the two input-node voltages to be nearly equal; this is the virtual-short approximation.

Explanation: Negative feedback holds the inverting node near the grounded non-inverting input voltage, although there is no direct physical ground connection at that node.

Explanation: Vp,max=SR/(2 pi f)=10^6/(2 pi×10^5)≈1.59 V.

Explanation: Output offset due to input offset is approximately noise gain times Vos: 101×1 mV=101 mV.

Explanation: Placing the diode within an op-amp feedback arrangement allows accurate rectification of signals much smaller than a normal diode's forward drop.

Explanation: The parallel resistor provides finite DC feedback, preventing tiny offsets and bias currents from integrating indefinitely and driving the output into saturation.

Explanation: The ideal differentiator's gain rises with frequency, making it highly sensitive to high-frequency noise and stability problems; practical designs limit this gain.

Explanation: With zero differential input, an ideal matched pair shares the 1 mA tail current equally, so each transistor carries about 0.5 mA.

Explanation: Each transistor carries IT/2 at balance, giving gm=IT/(2VT). For differential excitation, the single-ended collector-current change is gm(vd/2), so the effective differential transconductance is IT/(4VT).

Explanation: CMRR=1000/0.05=20000. Therefore CMRR(dB)=20log10(20000)≈86 dB.

Explanation: The mirror redirects one branch-current variation and combines it with the other branch, producing a single-ended output with enhanced gain.

Explanation: The reference current supplies the diode-connected transistor collector current plus the base currents of the mirror transistors, producing finite-beta error.

Explanation: The Wilson topology uses feedback to reduce base-current-related error and generally raises output resistance compared with a simple mirror.

Explanation: Emitter degeneration in the Widlar arrangement allows currents much smaller than the reference current without requiring impractically large on-chip resistors.

Explanation: A high tail resistance makes total current less sensitive to common-mode voltage changes, reducing common-mode gain and improving CMRR.

Explanation: Vo=Aol(V+-V-)=100000×50 microvolts=5 V.

Explanation: Closed-loop bandwidth is approximately unity-gain frequency divided by noise gain: 10 MHz/20=500 kHz.

Explanation: SRmin=2πfVp=2π×100000×5≈3.14×10^6 V/s=3.14 V/microsecond.

Explanation: The common-mode input range defines allowable common movement of the input terminals while maintaining proper input-stage operation.

Explanation: A real output stage cannot generally drive exactly to or beyond its supply rails, and load current can further restrict available output swing.

Explanation: Rail-to-rail architectures extend input common-mode range and/or output swing close to the supply rails, useful at low supply voltages.

Explanation: High PSRR means variations on the power rails cause relatively little input-referred or output error.

Explanation: With current applied to the inverting summing node, the feedback resistor produces an output voltage proportional to input current.

Explanation: For the conventional inverting TIA, Vo=-IinRf=-(20 microampere)(100 kOhm)=-2 V.

Explanation: The exponential junction law allows an op-amp feedback circuit to produce an output proportional to the logarithm of input current or voltage.

Explanation: By placing an exponential junction in the input path and using linear feedback, the circuit can generate an exponential, or antilogarithmic, transfer.

Explanation: During sample mode the capacitor charges to the input level; during hold mode it retains that voltage as closely as practical.

Explanation: Leakage currents and finite storage cause the held capacitor voltage to change slowly; this rate is called droop.

Explanation: sin²(theta)=[1-cos(2theta)]/2, so squaring a sinusoid produces a DC term and a second-harmonic component.

Explanation: A VCO converts a control voltage into a corresponding change in oscillation frequency and is widely used in modulation and PLL systems.

Explanation: The phase detector compares reference and feedback phases; after loop filtering, its error signal controls the VCO to establish lock.

Explanation: For a voltage ratio, 80 dB corresponds to 10^(80/20)=10000.

Explanation: At the cutoff frequency of a first-order RC network, the magnitude is 1/sqrt(2), approximately 0.707 of the passband value.

Explanation: A first-order high-pass response rises at about 20 dB/decade below cutoff, so one decade below cutoff the asymptotic attenuation is about 20 dB.

Explanation: Each pole contributes approximately -20 dB/decade, so a two-pole low-pass response approaches -40 dB/decade.

Explanation: Bandwidth is fH-fL=11 kHz-9 kHz=2 kHz.

Explanation: For a narrowband band-pass filter, Q≈f0/BW=10000/500=20.

Explanation: A notch, or band-stop, filter produces strong rejection around a chosen frequency while passing frequencies on either side.

Explanation: The loop filter removes unwanted high-frequency detector components and determines important loop bandwidth and dynamic characteristics.

Explanation: In lock, feedback maintains the required frequency relationship and the phase error settles to a constant value appropriate to the loop.

Explanation: In lock, the divided output equals the reference, so fout/N=fref and fout=Nfref=50×100 kHz=5 MHz.

Explanation: Capture range describes the frequency range from which an unlocked loop can acquire synchronization with the input.

Explanation: Once lock is established, the loop can track input-frequency variation over its lock or hold-in range.

Explanation: Hysteresis width is the difference between the upper and lower thresholds: 2-(-2)=4 V.

Explanation: A zero-crossing detector compares the input with a zero-volt reference and switches output polarity when the input crosses zero.

Explanation: The capacitor repeatedly charges and discharges between hysteresis thresholds, causing the comparator output to switch and sustain oscillation.

Explanation: Increasing timing resistance increases the RC charging/discharging time, so the oscillation period grows and frequency decreases.

Explanation: A normalized second-order Butterworth section has Q=1/sqrt(2), approximately 0.707, giving a maximally flat magnitude response.

Explanation: The Butterworth approximation is designed for a maximally flat passband magnitude response without ripple.

Explanation: Chebyshev Type I uses equal-ripple passband behavior to obtain a steeper transition than a comparable Butterworth design.

Explanation: Bessel responses are valued for nearly constant group delay and good transient behavior, helping preserve pulse and waveform shape.

Explanation: Class-AB operation lies between class A and class B; each device conducts for more than half a cycle but less than the full cycle.

Explanation: The temperature rise is P×theta=3×20=60 degrees C. Adding 30 degrees C ambient gives an estimated junction temperature of 90 degrees C.

Explanation: A monostable circuit has one stable state and one temporary quasi-stable state entered after triggering.

Explanation: An astable multivibrator has no stable state and continuously alternates between two states, generating a periodic waveform.

Explanation: A bistable circuit can remain indefinitely in either of two stable states until an external trigger causes a transition.

Explanation: For ideal class-B push-pull operation at maximum sinusoidal output, eta_max=pi/4≈0.785 or 78.5%.

Explanation: The diode-capacitor feedback arrangement charges the storage capacitor to the input peak and ideally holds that level between larger peaks.

Explanation: A buffer isolates the storage capacitor from the load, reducing loading and helping the held peak voltage decay more slowly.

Explanation: A clamper shifts the entire waveform upward or downward by adding a DC component while ideally retaining the original peak-to-peak amplitude.

Explanation: For the stated ideal positive clipping reference, conduction begins at the +3 V threshold and limits further positive excursion.

Explanation: Limiter or clipper circuits use diode conduction to constrain waveform excursions above or below chosen threshold levels.

Explanation: Op-amp feedback compensates much of the diode threshold error, allowing accurate rectification of low-level analog signals.

Explanation: The mean value of a full-wave rectified sine over one period is 2Vm/pi.

Explanation: Vavg=2Vm/pi=20/pi≈6.37 V.

Explanation: An RMS-to-DC converter performs the nonlinear operations needed to represent the effective or heating value of an AC waveform as a DC level.

Explanation: For a sine wave, Vrms=Vp/sqrt(2)=14.14/1.414≈10 V.

Explanation: Acquisition time measures how long the circuit needs to charge its hold capacitor and settle to the new sampled input within a specified error.

Explanation: For a capacitor, dV/dt=I/C=10 nA/1 nF=10 V/s.

Explanation: Average current equals charge per cycle multiplied by cycles per second: Iavg=Qf=Cf(V1-V2).

Explanation: With average current I=CfV, comparison with I=V/R gives Req=1/(Cf).

Explanation: Req=1/(Cf)=1/(10×10^-12×100×10^3)=1×10^6 ohm=1 MOhm.

Explanation: Chopper techniques modulate low-frequency signals away from the region dominated by offset and flicker noise, then demodulate them after amplification.

Explanation: Flicker noise is commonly called 1/f noise because its spectral density increases toward lower frequencies.

Explanation: White noise is modeled as having approximately flat power spectral density over the frequency band of interest.

Explanation: The standard resistor thermal-noise relation is mean-square voltage vn^2=4kTRB.

Explanation: Mean-square white noise is proportional to bandwidth, so RMS noise is proportional to sqrt(B). Increasing B fourfold doubles RMS noise.

Explanation: Noise figure compares input and output SNR and indicates how much additional noise the amplifier effectively contributes.

Explanation: Noise figure in decibels is SNRin(dB)-SNRout(dB)=40-34=6 dB.

Explanation: For a purely resistive Thevenin source, maximum load power occurs when RL=Rs.

Explanation: High input resistance draws little current from the source, minimizing loading and preserving the source voltage.

Explanation: Low output resistance minimizes voltage drop inside the amplifier when load current flows and improves voltage delivery to the load.

Explanation: Removing a twig separates the tree into two parts; the removed twig together with links reconnecting those parts forms its fundamental cut-set.