DRDO MCQs

Explanation: In a ripple-carry adder, a carry may propagate serially through all four stages. The approximate worst-case carry delay is 4 × 12 ns = 48 ns.

Explanation: Carry look-ahead forms carry signals from generate and propagate terms in parallel, reducing the delay associated with a ripple-carry chain.

Explanation: A carry is generated by the bit position regardless of carry-in when both Ai and Bi are 1, hence Gi = AiBi.

Explanation: Signed overflow occurs when operands with the same sign produce a result with the opposite sign. For two positive operands, a negative-sign result indicates overflow.

Explanation: For two's-complement addition, overflow equals the XOR of the carry into the most significant sign bit and the carry out of that bit.

Explanation: A Schmitt-trigger input uses different rising and falling switching thresholds, creating hysteresis that improves immunity to slowly varying or noisy inputs.

Explanation: When disabled, a tri-state output enters a high-impedance (Hi-Z) state so that it effectively disconnects from a shared bus.

Explanation: Disabled tri-state outputs present high impedance, allowing several devices to share conductors while preventing normal operation from having multiple active drivers at once.

Explanation: Opposing active drivers on the same line create bus contention, potentially causing excessive current and an undefined bus voltage.

Explanation: NMH = 4.4 − 3.2 = 1.2 V. It represents the allowable HIGH-level noise before the receiving input may no longer be guaranteed HIGH.

Explanation: Fan-out based on LOW-state current is IOL(max)/IIL = 16/1.6 = 10 loads.

Explanation: Minterms 1, 3, 5, and 7 are exactly the input combinations for which C=1, independent of A and B. Therefore F=C.

Explanation: A static-1 hazard is an unwanted 1→0→1 glitch caused by unequal propagation delays along different logic paths.

Explanation: In a Moore FSM, outputs are functions of state only. In a Mealy FSM, outputs are functions of both present state and current inputs.

Explanation: Because Mealy outputs can depend directly on current inputs, some output distinctions that require separate Moore states can be represented without adding states.

Explanation: A single parity check changes whenever an odd number of bits are inverted, so all odd-number error patterns are detected; even-number patterns can escape detection.

Explanation: Hamming SEC requires 2^r ≥ m+r+1. With m=11, r=4 gives 16 ≥ 11+4+1 = 16, so four parity bits are sufficient.

Explanation: A code with dmin=3 can correct floor((dmin−1)/2)=1 error. It can detect up to two errors, but ordinary Hamming decoding cannot reliably correct two.

Explanation: A PLA generally has programmable AND and programmable OR arrays, providing more flexible sum-of-products implementation than a PAL with a fixed OR structure.

Explanation: A conventional PAL has a programmable AND plane feeding a fixed OR plane, while a PLA normally allows both planes to be programmed.

Explanation: The insulated MOS gate draws essentially no DC input current ideally; practical devices have small leakage and transient charging current.

Explanation: A common approximation is Pdynamic ≈ αCLVDD²f, where α is switching activity. Thus power rises strongly with supply voltage and switching frequency.

Explanation: The receiving flip-flop needs stable data before the clock edge, so Tclk ≥ 18 ns + 2 ns = 20 ns under the stated assumptions.

Explanation: Clock skew is the difference in arrival time of the same clock edge at different sequential elements.

Explanation: At 2 MHz, one clock period is 0.5 microsecond. Sixteen clock periods therefore require 16 × 0.5 = 8 microseconds.

Explanation: A serial-in parallel-out (SIPO) register accepts bits sequentially and makes the stored bits available simultaneously at parallel outputs.

Explanation: A parallel-in serial-out (PISO) register loads a word in parallel and then shifts its bits out serially.

Explanation: The organization 2K × 16 means 2048 addressable words, each 16 bits wide. Therefore 16 data lines are required for a parallel word transfer.

Explanation: Setup time requires data to be stable for 3 ns before the active edge, and hold time requires it to remain stable for 1 ns after the edge.

Explanation: A timing violation can leave a bistable element temporarily between valid logic states. This metastable condition eventually resolves, but its resolution time is not precisely predictable.

Explanation: The first flip-flop may become metastable, while the second provides additional resolution time before the signal is used by downstream synchronous logic, greatly reducing failure probability.

Explanation: Starting with 0001, successive left cyclic shifts give 0010, 0100, and then 1000 after three clock pulses.

Explanation: A Johnson or twisted-ring counter feeds the complemented last-stage output back to the first stage and normally produces 2n distinct states.

Explanation: A standard n-stage Johnson counter has 2n states, so five stages provide 10 distinct states.

Explanation: In a synchronous counter, all flip-flops receive the clock together and combinational logic determines which stages toggle. This avoids cumulative ripple clocking between stages.

Explanation: 0111 is decimal 7. Incrementing by one gives decimal 8, represented by 1000 in four-bit binary.

Explanation: An asynchronous clear directly forces the stored state to the reset value independent of the normal clock transition.

Explanation: Selecting one of four chips requires log2(4)=2 selection bits. The lower 10 address bits address locations within each 1K chip.

Explanation: A DRAM cell stores data as capacitor charge that leaks with time, so rows must be periodically refreshed.

Explanation: SRAM uses bistable circuitry and normally offers faster access without refresh, although it uses more devices per bit and has lower density than DRAM.

Explanation: EEPROM is electrically erasable and programmable. Traditional EPROM requires ultraviolet light for erasure, while EEPROM supports electrical rewriting.

Explanation: Flash memory is generally organized so erase operations affect blocks or sectors, enabling higher density than conventional byte-oriented EEPROM implementations.

Explanation: An ideal 10-bit converter has 2^10=1024 steps. Thus one LSB = 5.12 V/1024 = 0.005 V = 5 mV.

Explanation: A SAR converter determines one output bit per successive approximation step, so an ideal 12-bit conversion requires about 12 bit decisions.

Explanation: A conventional n-bit flash ADC uses one comparator for each decision threshold between adjacent output levels, giving 2^n − 1 comparators.

Explanation: For n=8, the flash ADC comparator count is 2^8 − 1 = 255.

Explanation: An R-2R ladder is constructed using only R and 2R values, simplifying resistor matching and IC implementation compared with a wide range of binary-weighted resistor values.

Explanation: For an unsigned 4-bit DAC, code value increases from 0000 to the maximum code 1111, so 1111 produces the largest ideal output.

Explanation: The sample-and-hold captures the instantaneous analog input and holds it nearly constant so the ADC sees a stable value while conversion is in progress.

Explanation: A BCD digit is valid only from 0000 through 1001. When the binary digit sum exceeds 9, adding 0110₂ corrects the result and generates the appropriate decimal carry.

Explanation: 5+7=12. The initial binary sum 1100 is invalid BCD, so adding 0110 gives 1 0010. Thus the BCD result is 0001 0010, representing decimal 12.

Explanation: Excess-3 represents a decimal digit by adding 3 and encoding the result in four-bit binary. For 6, 6+3=9, giving 1001.

Explanation: Excess-3 is a self-complementing code: complementing all four bits of a digit code gives the Excess-3 code for the 9's complement of that decimal digit.

Explanation: An Arithmetic Logic Unit is a combinational subsystem that performs selected arithmetic and logical operations on binary operands.

Explanation: A barrel shifter uses combinational selection networks to shift or rotate an entire word by a selected number of positions without requiring one clock per bit position.

Explanation: An n-to-2^n decoder generates one output for each possible input minterm. The required minterm outputs can then be ORed to realize an SOP function.

Explanation: Six inputs select 2^6=64 addresses. Each address stores 4 output bits, so total storage is 64×4=256 bits.

Explanation: The minimum n satisfies 2^n≥8. Since 2^3=8, three binary state bits are sufficient.

Explanation: A maximal-length LFSR generates a pseudorandom sequence containing every nonzero n-bit state once per period, giving 2^n−1 states.

Explanation: For n=4, a maximal-length LFSR period is 2^4−1=15 states.

Explanation: With XOR feedback, an all-zero register generally produces zero feedback, so every subsequent state remains all zero unless external logic forces the LFSR out of that state.

Explanation: CRC arithmetic represents bit strings as polynomials with binary coefficients and performs division using modulo-2 operations over GF(2).

Explanation: Over GF(2), addition and subtraction are identical and correspond to XOR; there are no carries or borrows.

Explanation: The remainder from division by a degree-r generator polynomial has at most r bits, so a degree-4 generator produces four CRC bits.

Explanation: An open-collector output provides a transistor path to LOW when active. When inactive, the external pull-up resistor establishes the HIGH level.

Explanation: A PROM is manufactured with a fixed decoding structure and user-programmable storage connections, allowing a desired data pattern or truth table to be permanently programmed.

Explanation: Four binary inputs have 2^4=16 possible combinations. A 4-input LUT stores one output value for each combination, so 16 configuration bits represent an arbitrary four-variable Boolean function.

Explanation: FPGAs combine configurable logic resources with programmable interconnect, allowing the configured circuit's signal paths to be established after manufacture.

Explanation: Substituting the values gives Tclk ≥ 2+11+2+1 = 16 ns.

Explanation: fmax=1/Tmin=1/(16 ns)=62.5 MHz.

Explanation: Hold analysis checks that new data cannot reach the destination flip-flop too soon after the active clock edge, so minimum path delay is critical.

Explanation: A synchronous reset is sampled as part of the clocked logic operation and therefore takes effect at the relevant active clock edge.

Explanation: One-hot encoding assigns one flip-flop to each state and keeps exactly one state bit asserted, so eight states require eight state flip-flops.

Explanation: Because any active open-collector transistor can pull the common node LOW while inactive outputs release it, compatible outputs can share a pull-up line to implement wired logic.

Explanation: A one-position arithmetic right shift moves each bit toward lower significance while preserving the sign, corresponding to signed division by 2 under the stated conditions.

Explanation: Cascaded magnitude comparison requires greater-than, equal-to, and less-than status so higher-order groups can determine the overall relation correctly.

Explanation: Without a valid indication, the encoded output corresponding to no active input can be ambiguous with the code for a legitimate input. VALID indicates that an asserted input exists.

Explanation: For an active-LOW decoder, assertion is represented by logic 0, so the selected output is LOW and unselected outputs remain HIGH.

Explanation: Four first-stage 4-to-1 multiplexers select from 16 total inputs, and a second-stage 4-to-1 multiplexer selects one of their four outputs.

Explanation: A static-0 hazard is a temporary 0→1→0 glitch caused by unequal propagation delays when the correct steady output should remain LOW.

Explanation: A dynamic hazard occurs when unequal delays through multiple paths cause several output transitions before the circuit reaches its final correct value.

Explanation: A carry propagates through the entire group only if every bit position propagates it, so the group-propagate condition is the product P0P1P2P3.

Explanation: A borrow is needed whenever the bit being subtracted, including any incoming borrow effect, exceeds the available minuend value at that position.

Explanation: 14+5=19, which exceeds the 4-bit unsigned maximum of 15. A saturating adder clamps the result to 1111 rather than wrapping around.

Explanation: In 8-bit two's-complement representation the range is −128 to +127, and the code 10000000 represents the minimum value, −128.

Explanation: An arithmetic right shift preserves the sign of a two's-complement value by filling vacated most-significant positions with copies of the sign bit.

Explanation: Monotonicity means the analog output never reverses direction when the input code changes monotonically in one direction.

Explanation: Settling time is measured from a code transition until the analog output reaches and stays within a specified tolerance around its final value.

Explanation: Eight destinations require log2(8)=3 binary select inputs.

Explanation: A negative-edge-triggered device responds to the falling clock transition, from logic HIGH to logic LOW.

Explanation: Because the next D input is the complement of the current Q, each active edge loads the opposite state. The D flip-flop therefore behaves as a toggle element.

Explanation: Four flip-flops can represent 16 binary states. A MOD-10 sequence uses 10 of them, leaving 16−10=6 unused states.

Explanation: A self-starting counter has next-state logic that directs unused states back into the valid sequence, preventing permanent lockout.

Explanation: Dual-port memory provides two access interfaces, enabling two agents or datapaths to access a shared memory array with suitable arbitration or port rules.

Explanation: FIFO means First-In, First-Out: entries leave the buffer in the same order in which they entered.

Explanation: FIFO control logic tracks read and write positions and derives EMPTY and FULL conditions to prevent invalid reads and overwriting of unread data.

Explanation: Dual-slope conversion integrates the input over a defined interval; choosing the interval appropriately can strongly reject periodic interference such as 50/60 Hz mains noise.

Explanation: DNL measures how much each actual transition step or code-bin width differs from the ideal one-LSB size.

Explanation: A missing code is an output value that the converter skips entirely as the analog input is swept through its range, often associated with excessive DNL.

Explanation: At thermal equilibrium, the product of electron and hole concentrations equals the square of the intrinsic carrier concentration: np = ni².