Flip-Flops MCQs

Practice Flip-Flops MCQs with four options, answers and explanations for focused Electronics & Telecommunication Engineering revision.

Question 1

Digital ElectronicsFlip-Flops

Which flip-flop has no invalid input combination in its basic two-input operation and toggles when both inputs are HIGH?

ASR flip-flop
BJK flip-flop
CD flip-flop
DT flip-flop with two independent inputs

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Correct Answer: B. JK flip-flop

Explanation: The JK flip-flop removes the basic SR forbidden condition; with J=K=1 it toggles.

Reference: JK flip-flop operation

Question 2

Digital ElectronicsFlip-Flops

A D flip-flop is commonly used to store how many bits?

A1 bit
B2 bits
C4 bits
D8 bits

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Correct Answer: A. 1 bit

Explanation: A single D flip-flop stores one binary state, corresponding to one bit.

Reference: D flip-flop fundamentals

Question 3

Digital ElectronicsFlip-Flops

For a JK flip-flop, if J = 1 and K = 1, the next state is?

AAlways 0
BAlways 1
CThe complement of the present state
DEqual to the present state

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Correct Answer: C. The complement of the present state

Explanation: With J = K = 1, a JK flip-flop toggles, so Q(next) is the complement of Q(present).

Reference: Standard digital electronics: JK flip-flop characteristic

Question 4

Digital ElectronicsFlip-Flops

To make a JK flip-flop behave like a T flip-flop, J and K should be connected so that?

AJ = 0 and K = 1 permanently
BJ = K = T
CJ = T and K = 0
DJ = 1 and K = T complement

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Correct Answer: B. J = K = T

Explanation: A JK flip-flop toggles when J = K = 1 and holds when J = K = 0. Connecting J and K together to T reproduces T flip-flop operation.

Reference: Standard digital electronics: flip-flop conversion

Question 5

Digital ElectronicsFlip-Flops

The excitation required for an SR flip-flop to change from Q = 0 to Q(next) = 1 is?

AS = 0, R = 0
BS = 0, R = 1
CS = 1, R = 0
DS = 1, R = 1

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Correct Answer: C. S = 1, R = 0

Explanation: To set an SR flip-flop from 0 to 1, the set input is asserted and reset is deasserted: S = 1, R = 0.

Reference: Standard digital electronics: SR flip-flop excitation

Question 6

Digital ElectronicsFlip-Flops

The race-around condition in a level-triggered JK flip-flop can occur when?

AJ = K = 0
BJ = 0, K = 1
CJ = K = 1 and the clock pulse is sufficiently wide
DJ = 1, K = 0 only

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Correct Answer: C. J = K = 1 and the clock pulse is sufficiently wide

Explanation: When J = K = 1, repeated toggling can occur during a sufficiently long active clock level if the propagation delay permits multiple changes.

Reference: Standard digital electronics: race-around condition

Question 7

Digital ElectronicsFlip-Flops

A common method of avoiding race-around in a JK flip-flop is to use?

AA master-slave or edge-triggered flip-flop
BA larger supply voltage only
CAn OR gate at the output
DA resistor in series with every input

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Correct Answer: A. A master-slave or edge-triggered flip-flop

Explanation: Master-slave or edge-triggered operation restricts the effective state transition and prevents repeated toggling during one clock interval.

Reference: Standard digital electronics: JK flip-flops

Question 8

Digital ElectronicsFlip-Flops

In an asynchronous clear input of a flip-flop, the term asynchronous means that clearing can occur?

AWithout waiting for an active clock edge
BOnly at the next clock edge
COnly when data input is HIGH
DOnly after two clock cycles

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Correct Answer: A. Without waiting for an active clock edge

Explanation: An asynchronous clear directly forces the stored state to the reset value independent of the normal clock transition.

Reference: Standard digital electronics: asynchronous reset

Question 9

Digital ElectronicsFlip-Flops

Unlike an asynchronous reset, a synchronous reset normally changes a flip-flop’s state?

AOnly in association with the active clock edge
BImmediately regardless of the clock
COnly when power is removed
DOnly after the clock stops

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Correct Answer: A. Only in association with the active clock edge

Explanation: A synchronous reset is sampled as part of the clocked logic operation and therefore takes effect at the relevant active clock edge.

Reference: Standard digital electronics: synchronous reset

Question 10

Digital ElectronicsFlip-Flops

For a negative-edge-triggered flip-flop, the input is sampled primarily at which clock transition?

ALOW-to-HIGH
BHIGH-to-LOW
COnly while clock remains HIGH
DOnly while clock remains LOW

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Correct Answer: B. HIGH-to-LOW

Explanation: A negative-edge-triggered device responds to the falling clock transition, from logic HIGH to logic LOW.

Reference: Standard digital electronics: edge-triggered flip-flops

Question 11

Digital ElectronicsFlip-Flops

A D flip-flop has D=Q̅ connected externally. Ignoring asynchronous controls, what behavior occurs on each active clock edge?

AIt toggles
BIt always resets
CIt always sets
DIt retains its state forever

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Correct Answer: A. It toggles

Explanation: Because the next D input is the complement of the current Q, each active edge loads the opposite state. The D flip-flop therefore behaves as a toggle element.

Reference: Standard digital electronics: D flip-flop feedback