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Digital Electronics MCQs

Practice Digital Electronics MCQs from fundamental concepts through intermediate, advanced and application-oriented questions. Each page contains up to 100 questions with answers and explanations where available.

Question 101
Digital ElectronicsDigital Interfaces

If two push-pull digital outputs connected to the same bus are simultaneously enabled, one driving HIGH and the other LOW, the condition is called?

  • ABus contention
  • BGray transition
  • CClock skew
  • DDynamic refresh
Report an error
Correct Answer: A. Bus contention
Explanation: Opposing active drivers on the same line create bus contention, potentially causing excessive current and an undefined bus voltage.
Reference: Standard digital electronics: bus contention
Question 105
Digital ElectronicsLogic Hazards

In a static-1 hazard, the output of a combinational circuit may momentarily do what even though it should remain at logic 1?

  • ARemain permanently LOW
  • BDrop briefly to logic 0
  • COscillate indefinitely
  • DBecome high-impedance
Report an error
Correct Answer: B. Drop briefly to logic 0
Explanation: A static-1 hazard is an unwanted 1→0→1 glitch caused by unequal propagation delays along different logic paths.
Reference: Standard digital electronics: static hazards
Question 107
Digital ElectronicsArithmetic Circuits

A 4-bit binary adder uses identical ripple-carry full-adder stages. If each stage requires 12 ns for its carry output to become valid after carry-in changes, approximately what is the worst-case carry propagation time through all four stages?

  • A12 ns
  • B24 ns
  • C36 ns
  • D48 ns
Report an error
Correct Answer: D. 48 ns
Explanation: In a ripple-carry adder, a carry may propagate serially through all four stages. The approximate worst-case carry delay is 4 × 12 ns = 48 ns.
Reference: Standard digital electronics: ripple-carry adder delay
Question 108
Digital ElectronicsArithmetic Circuits

The principal purpose of carry look-ahead logic in a binary adder is to?

  • AReduce carry propagation delay
  • BConvert binary to Gray code
  • CStore the carry permanently
  • DReduce the number of sum bits
Report an error
Correct Answer: A. Reduce carry propagation delay
Explanation: Carry look-ahead forms carry signals from generate and propagate terms in parallel, reducing the delay associated with a ripple-carry chain.
Reference: Standard digital electronics: carry look-ahead
Question 110
Digital ElectronicsSigned Arithmetic

In two’s-complement signed arithmetic, adding two positive n-bit numbers produces an overflow when?

  • AThe result has sign bit 1 even though both operands have sign bit 0
  • BA carry is produced from the LSB
  • CThe result is zero
  • DThe carry-in to the LSB is 1
Report an error
Correct Answer: A. The result has sign bit 1 even though both operands have sign bit 0
Explanation: Signed overflow occurs when operands with the same sign produce a result with the opposite sign. For two positive operands, a negative-sign result indicates overflow.
Reference: Standard digital electronics: two's-complement overflow
Question 111
Digital ElectronicsSigned Arithmetic

In two’s-complement addition, overflow can be detected by XORing which two carry signals?

  • ACarry into and carry out of the sign bit
  • BCarry into bit 0 and bit 1
  • CTwo successive clock carries
  • DCarry out and borrow out
Report an error
Correct Answer: A. Carry into and carry out of the sign bit
Explanation: For two's-complement addition, overflow equals the XOR of the carry into the most significant sign bit and the carry out of that bit.
Reference: Standard digital electronics: overflow detection
Question 112
Digital ElectronicsDigital Interfaces

Which property distinguishes a Schmitt-trigger digital input from an ordinary single-threshold input?

  • AIt has two switching thresholds and hysteresis
  • BIt stores one bit indefinitely
  • CIt always inverts the signal twice
  • DIt requires no supply voltage
Report an error
Correct Answer: A. It has two switching thresholds and hysteresis
Explanation: A Schmitt-trigger input uses different rising and falling switching thresholds, creating hysteresis that improves immunity to slowly varying or noisy inputs.
Reference: Standard digital electronics: Schmitt trigger
Question 114
Digital ElectronicsDigital Interfaces

Why are tri-state buffers commonly used on a shared digital bus?

  • ATo allow multiple devices to be connected while only one enabled driver controls the bus at a time
  • BTo make every device drive the bus simultaneously
  • CTo convert the bus to analog
  • DTo eliminate the need for logic levels
Report an error
Correct Answer: A. To allow multiple devices to be connected while only one enabled driver controls the bus at a time
Explanation: Disabled tri-state outputs present high impedance, allowing several devices to share conductors while preventing normal operation from having multiple active drivers at once.
Reference: Standard digital electronics: bus interfacing
Question 115
Digital ElectronicsLogic Families

In ideal CMOS logic under steady DC conditions, the input current is approximately?

  • AVery large
  • BApproximately zero except leakage
  • CEqual to output current
  • DFixed at 1 mA
Report an error
Correct Answer: B. Approximately zero except leakage
Explanation: The insulated MOS gate draws essentially no DC input current ideally; practical devices have small leakage and transient charging current.
Reference: Standard digital electronics: CMOS input characteristics
Question 117
Digital ElectronicsSequential Timing

A synchronous finite-state machine has a maximum combinational-path delay of 18 ns and flip-flop setup time of 2 ns. Ignoring clock skew and clock-to-Q delay, the clock period must be at least?

  • A9 ns
  • B16 ns
  • C18 ns
  • D20 ns
Report an error
Correct Answer: D. 20 ns
Explanation: The receiving flip-flop needs stable data before the clock edge, so Tclk ≥ 18 ns + 2 ns = 20 ns under the stated assumptions.
Reference: Standard digital electronics: synchronous timing
Question 119
Digital ElectronicsFinite State Machines

Which statement correctly distinguishes a Moore machine from a Mealy machine?

  • AMoore output depends only on present state, while Mealy output can depend on present state and input
  • BMoore has no states
  • CMealy output depends only on the clock frequency
  • DMoore cannot be implemented with flip-flops
Report an error
Correct Answer: A. Moore output depends only on present state, while Mealy output can depend on present state and input
Explanation: In a Moore FSM, outputs are functions of state only. In a Mealy FSM, outputs are functions of both present state and current inputs.
Reference: Standard digital electronics: Moore and Mealy machines
Question 120
Digital ElectronicsFinite State Machines

For the same behavioral specification, a Mealy state machine can often use fewer states than an equivalent Moore machine because?

  • AIts outputs may respond directly to inputs as well as state
  • BIt contains no combinational logic
  • CIt does not use a clock
  • DIt stores multiple analog levels
Report an error
Correct Answer: A. Its outputs may respond directly to inputs as well as state
Explanation: Because Mealy outputs can depend directly on current inputs, some output distinctions that require separate Moore states can be represented without adding states.
Reference: Standard digital electronics: FSM realization
Question 121
Digital ElectronicsError Detection Codes

A parity system using one parity bit can reliably detect which class of errors in a transmitted word?

  • AAny odd number of bit errors
  • BEvery even number of bit errors
  • CAll burst errors regardless of length
  • DEvery possible error pattern
Report an error
Correct Answer: A. Any odd number of bit errors
Explanation: A single parity check changes whenever an odd number of bits are inverted, so all odd-number error patterns are detected; even-number patterns can escape detection.
Reference: Standard digital electronics: parity
Question 123
Digital ElectronicsError Control Codes

A standard Hamming code with minimum Hamming distance dmin=3 can?

  • ACorrect one bit error but not guarantee correction of two bit errors
  • BCorrect any two bit errors
  • CCorrect any three bit errors
  • DOnly detect one bit error and correct none
Report an error
Correct Answer: A. Correct one bit error but not guarantee correction of two bit errors
Explanation: A code with dmin=3 can correct floor((dmin−1)/2)=1 error. It can detect up to two errors, but ordinary Hamming decoding cannot reliably correct two.
Reference: Standard digital electronics: Hamming distance
Question 124
Digital ElectronicsProgrammable Logic Devices

In a programmable logic array (PLA), which logic planes are normally programmable?

  • AAND plane only
  • BOR plane only
  • CBoth AND and OR planes
  • DNeither plane
Report an error
Correct Answer: C. Both AND and OR planes
Explanation: A PLA generally has programmable AND and programmable OR arrays, providing more flexible sum-of-products implementation than a PAL with a fixed OR structure.
Reference: Standard digital electronics: PLA architecture
Question 125
Digital ElectronicsProgrammable Logic Devices

Compared with a PLA, a traditional PAL typically uses?

  • AProgrammable AND array and fixed OR array
  • BFixed AND array and programmable OR array
  • CProgrammable RAM cells only
  • DNo AND-OR structure
Report an error
Correct Answer: A. Programmable AND array and fixed OR array
Explanation: A conventional PAL has a programmable AND plane feeding a fixed OR plane, while a PLA normally allows both planes to be programmed.
Reference: Standard digital electronics: PAL architecture
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Question 126
Digital ElectronicsClock Domain Crossing

Why is a two-flip-flop synchronizer commonly used when a single-bit asynchronous signal enters a synchronous clock domain?

  • ATo reduce the probability that metastability propagates into downstream logic
  • BTo double the asynchronous signal frequency
  • CTo convert binary to BCD
  • DTo remove the clock
Report an error
Correct Answer: A. To reduce the probability that metastability propagates into downstream logic
Explanation: The first flip-flop may become metastable, while the second provides additional resolution time before the signal is used by downstream synchronous logic, greatly reducing failure probability.
Reference: Standard digital electronics: asynchronous input synchronization
Question 130
Digital ElectronicsCounters

A synchronous binary counter differs fundamentally from a ripple counter because in a synchronous counter?

  • AAll flip-flops are clocked by the common clock
  • BOnly the first flip-flop receives a clock
  • CEach stage is triggered only by the previous stage output
  • DNo flip-flops are used
Report an error
Correct Answer: A. All flip-flops are clocked by the common clock
Explanation: In a synchronous counter, all flip-flops receive the clock together and combinational logic determines which stages toggle. This avoids cumulative ripple clocking between stages.
Reference: Standard digital electronics: synchronous counters
Question 132
Digital ElectronicsFlip-Flops

In an asynchronous clear input of a flip-flop, the term asynchronous means that clearing can occur?

  • AWithout waiting for an active clock edge
  • BOnly at the next clock edge
  • COnly when data input is HIGH
  • DOnly after two clock cycles
Report an error
Correct Answer: A. Without waiting for an active clock edge
Explanation: An asynchronous clear directly forces the stored state to the reset value independent of the normal clock transition.
Reference: Standard digital electronics: asynchronous reset
Question 133
Digital ElectronicsShift Registers

A 16-bit shift register is clocked at 2 MHz. Ignoring loading overhead, how long does it take to shift 16 serial bits through 16 clock periods?

  • A1 microsecond
  • B4 microseconds
  • C8 microseconds
  • D16 microseconds
Report an error
Correct Answer: C. 8 microseconds
Explanation: At 2 MHz, one clock period is 0.5 microsecond. Sixteen clock periods therefore require 16 × 0.5 = 8 microseconds.
Reference: Standard digital electronics: serial shifting
Question 137
Digital ElectronicsSequential Timing

A positive-edge-triggered D flip-flop has setup time 3 ns and hold time 1 ns. For reliable operation, the D input must be stable for at least which interval around the active clock edge?

  • A3 ns before and 1 ns after
  • B1 ns before and 3 ns after
  • COnly 3 ns after
  • DOnly at the exact clock instant
Report an error
Correct Answer: A. 3 ns before and 1 ns after
Explanation: Setup time requires data to be stable for 3 ns before the active edge, and hold time requires it to remain stable for 1 ns after the edge.
Reference: Standard digital electronics: setup and hold time
Question 138
Digital ElectronicsSequential Timing

If the setup or hold requirement of a flip-flop is violated, the flip-flop may temporarily enter which condition?

  • AMetastability
  • BPermanent tri-state
  • CFrequency lock
  • DQuantization
Report an error
Correct Answer: A. Metastability
Explanation: A timing violation can leave a bistable element temporarily between valid logic states. This metastable condition eventually resolves, but its resolution time is not precisely predictable.
Reference: Standard digital electronics: metastability
Question 140
Digital ElectronicsADC & DAC

Ignoring overhead, an ideal 12-bit successive-approximation ADC that performs one bit decision per clock requires approximately how many comparison steps for one conversion?

  • A6
  • B10
  • C12
  • D4096
Report an error
Correct Answer: C. 12
Explanation: A SAR converter determines one output bit per successive approximation step, so an ideal 12-bit conversion requires about 12 bit decisions.
Reference: Standard digital electronics: SAR conversion
Question 143
Digital ElectronicsADC & DAC

For an ideal R-2R ladder DAC, one major practical advantage over a binary-weighted-resistor DAC is that the ladder requires?

  • AOnly two resistor values
  • BNo resistors
  • CA different resistor for every possible code
  • DOnly capacitors
Report an error
Correct Answer: A. Only two resistor values
Explanation: An R-2R ladder is constructed using only R and 2R values, simplifying resistor matching and IC implementation compared with a wide range of binary-weighted resistor values.
Reference: Standard digital electronics: R-2R DAC
Question 145
Digital ElectronicsADC & DAC

A sample-and-hold circuit placed ahead of an ADC is primarily used to?

  • AKeep the analog input approximately constant during conversion
  • BGenerate the ADC clock
  • CStore the final digital code permanently
  • DIncrease the number of ADC bits automatically
Report an error
Correct Answer: A. Keep the analog input approximately constant during conversion
Explanation: The sample-and-hold captures the instantaneous analog input and holds it nearly constant so the ADC sees a stable value while conversion is in progress.
Reference: Standard digital electronics: sample-and-hold
Question 148
Digital ElectronicsMemory

Compared with DRAM, a typical SRAM cell is generally?

  • AFaster and does not require periodic refresh
  • BSlower and always requires refresh
  • CNonvolatile without power
  • DImplemented with one storage capacitor only
Report an error
Correct Answer: A. Faster and does not require periodic refresh
Explanation: SRAM uses bistable circuitry and normally offers faster access without refresh, although it uses more devices per bit and has lower density than DRAM.
Reference: Standard digital electronics: SRAM versus DRAM
Question 149
Digital ElectronicsMemory

Which nonvolatile memory can normally be electrically erased and rewritten at byte or small-unit granularity, unlike traditional UV-erasable EPROM?

  • AEEPROM
  • BSRAM
  • CDRAM
  • DRegister file only
Report an error
Correct Answer: A. EEPROM
Explanation: EEPROM is electrically erasable and programmable. Traditional EPROM requires ultraviolet light for erasure, while EEPROM supports electrical rewriting.
Reference: Standard digital electronics: EEPROM
Question 150
Digital ElectronicsMemory

Flash memory differs from conventional byte-erasable EEPROM mainly because flash is commonly erased in?

  • ABlocks or sectors
  • BSingle transistor terminals only
  • CClock cycles only
  • DAnalog voltage levels only
Report an error
Correct Answer: A. Blocks or sectors
Explanation: Flash memory is generally organized so erase operations affect blocks or sectors, enabling higher density than conventional byte-oriented EEPROM implementations.
Reference: Standard digital electronics: flash memory
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Question 151
Digital ElectronicsBCD Arithmetic

In 8421 BCD addition, if a 4-bit digit sum is greater than 1001₂ (decimal 9), which binary correction is added to obtain a valid BCD result?

  • A0011
  • B0110
  • C1001
  • D1010
Report an error
Correct Answer: B. 0110
Explanation: A BCD digit is valid only from 0000 through 1001. When the binary digit sum exceeds 9, adding 0110₂ corrects the result and generates the appropriate decimal carry.
Reference: Standard digital electronics: BCD addition
Question 153
Digital ElectronicsNumber Systems & Codes

The Excess-3 code for decimal digit 6 is?

  • A0110
  • B1001
  • C1010
  • D1100
Report an error
Correct Answer: B. 1001
Explanation: Excess-3 represents a decimal digit by adding 3 and encoding the result in four-bit binary. For 6, 6+3=9, giving 1001.
Reference: Standard digital electronics: Excess-3 code
Question 154
Digital ElectronicsNumber Systems & Codes

Which useful property does the Excess-3 decimal code possess?

  • AIt is self-complementing
  • BIt uses only three bits per decimal digit
  • CIt is a weighted 8421 code
  • DAdjacent values always differ by one bit
Report an error
Correct Answer: A. It is self-complementing
Explanation: Excess-3 is a self-complementing code: complementing all four bits of a digit code gives the Excess-3 code for the 9's complement of that decimal digit.
Reference: Standard digital electronics: Excess-3 properties
Question 155
Digital ElectronicsArithmetic Logic Units

A 4-bit ALU is designed to perform arithmetic and logic functions selected by control inputs. The term ALU stands for?

  • AArithmetic Logic Unit
  • BAsynchronous Latch Utility
  • CAnalog Level Unit
  • DAddress Logic Uplink
Report an error
Correct Answer: A. Arithmetic Logic Unit
Explanation: An Arithmetic Logic Unit is a combinational subsystem that performs selected arithmetic and logical operations on binary operands.
Reference: Standard digital electronics: ALU
Question 156
Digital ElectronicsData Path Circuits

A barrel shifter differs from a simple serial shift register because a barrel shifter can typically?

  • AShift or rotate a word by multiple bit positions in one combinational operation
  • BStore data without any logic gates
  • CConvert analog voltage directly to binary
  • DRefresh DRAM rows
Report an error
Correct Answer: A. Shift or rotate a word by multiple bit positions in one combinational operation
Explanation: A barrel shifter uses combinational selection networks to shift or rotate an entire word by a selected number of positions without requiring one clock per bit position.
Reference: Standard digital electronics: barrel shifter
Question 157
Digital ElectronicsDecoder Applications

To implement an arbitrary Boolean function of n input variables directly with a decoder and an OR gate, the decoder normally requires how many output minterm lines?

  • An
  • B2n
  • C2^n
  • Dn^2
Report an error
Correct Answer: C. 2^n
Explanation: An n-to-2^n decoder generates one output for each possible input minterm. The required minterm outputs can then be ORed to realize an SOP function.
Reference: Standard digital electronics: decoder realization of Boolean functions
Question 159
Digital ElectronicsFPGA

A 4-input lookup table (LUT) in an FPGA can directly represent any Boolean function of up to four variables because it stores how many truth-table output bits?

  • A4
  • B8
  • C16
  • D32
Report an error
Correct Answer: C. 16
Explanation: Four binary inputs have 2^4=16 possible combinations. A 4-input LUT stores one output value for each combination, so 16 configuration bits represent an arbitrary four-variable Boolean function.
Reference: Standard digital electronics: FPGA LUT
Question 160
Digital ElectronicsFPGA

In an FPGA, configurable logic blocks are interconnected primarily through?

  • AProgrammable routing resources
  • BFixed mechanical switches only
  • CAnalog transformers
  • DDRAM refresh lines only
Report an error
Correct Answer: A. Programmable routing resources
Explanation: FPGAs combine configurable logic resources with programmable interconnect, allowing the configured circuit's signal paths to be established after manufacture.
Reference: Standard digital electronics: FPGA architecture
Question 161
Digital ElectronicsSequential Timing

For a register-to-register synchronous path, Tcq=2 ns, maximum combinational delay=11 ns, setup time=2 ns, and worst-case clock uncertainty=1 ns. What minimum clock period is required using Tclk ≥ Tcq + Tcomb + Tsetup + Tuncertainty?

  • A12 ns
  • B14 ns
  • C16 ns
  • D18 ns
Report an error
Correct Answer: C. 16 ns
Explanation: Substituting the values gives Tclk ≥ 2+11+2+1 = 16 ns.
Reference: Standard digital electronics: maximum clock frequency timing
Question 163
Digital ElectronicsSequential Timing

A hold-time check in a synchronous register path is primarily concerned with which path characteristic?

  • AMinimum or contamination delay
  • BMaximum combinational delay only
  • CAverage propagation delay only
  • DPower-supply frequency
Report an error
Correct Answer: A. Minimum or contamination delay
Explanation: Hold analysis checks that new data cannot reach the destination flip-flop too soon after the active clock edge, so minimum path delay is critical.
Reference: Standard digital electronics: hold-time analysis
Question 164
Digital ElectronicsFlip-Flops

Unlike an asynchronous reset, a synchronous reset normally changes a flip-flop’s state?

  • AOnly in association with the active clock edge
  • BImmediately regardless of the clock
  • COnly when power is removed
  • DOnly after the clock stops
Report an error
Correct Answer: A. Only in association with the active clock edge
Explanation: A synchronous reset is sampled as part of the clocked logic operation and therefore takes effect at the relevant active clock edge.
Reference: Standard digital electronics: synchronous reset
Question 167
Digital ElectronicsLFSR & Sequence Generators

A maximal-length n-stage linear feedback shift register (LFSR), when configured with a primitive feedback polynomial and excluding the all-zero lock state, cycles through how many nonzero states?

  • An
  • B2n
  • C2^n - 1
  • D2^n
Report an error
Correct Answer: C. 2^n - 1
Explanation: A maximal-length LFSR generates a pseudorandom sequence containing every nonzero n-bit state once per period, giving 2^n−1 states.
Reference: Standard digital electronics: maximal-length LFSR
Question 169
Digital ElectronicsLFSR & Sequence Generators

Why is the all-zero state normally excluded from an XOR-feedback LFSR sequence?

  • AIt can become a locked state that continues producing zeros
  • BIt causes the supply voltage to double
  • CIt automatically changes to all ones
  • DIt destroys the clock generator
Report an error
Correct Answer: A. It can become a locked state that continues producing zeros
Explanation: With XOR feedback, an all-zero register generally produces zero feedback, so every subsequent state remains all zero unless external logic forces the LFSR out of that state.
Reference: Standard digital electronics: LFSR lock state
Question 170
Digital ElectronicsError Detection Codes

A cyclic redundancy check (CRC) treats a binary data sequence mathematically as?

  • AA polynomial over GF(2)
  • BA decimal floating-point number only
  • CAn analog waveform amplitude
  • DA Gray-code counter only
Report an error
Correct Answer: A. A polynomial over GF(2)
Explanation: CRC arithmetic represents bit strings as polynomials with binary coefficients and performs division using modulo-2 operations over GF(2).
Reference: Standard digital electronics: CRC
Question 171
Digital ElectronicsError Detection Codes

In modulo-2 polynomial division used for CRC generation, subtraction is performed using?

  • AXOR without borrow
  • BOrdinary decimal subtraction with borrow
  • CXNOR with carry
  • DTwo's-complement multiplication
Report an error
Correct Answer: A. XOR without borrow
Explanation: Over GF(2), addition and subtraction are identical and correspond to XOR; there are no carries or borrows.
Reference: Standard digital electronics: CRC modulo-2 arithmetic
Question 173
Digital ElectronicsDigital Interfaces

An open-collector logic output requires an external pull-up resistor mainly because the output stage can actively?

  • APull the line LOW but does not actively drive it HIGH
  • BDrive only HIGH and never LOW
  • CGenerate an analog sine wave
  • DStore a logic word
Report an error
Correct Answer: A. Pull the line LOW but does not actively drive it HIGH
Explanation: An open-collector output provides a transistor path to LOW when active. When inactive, the external pull-up resistor establishes the HIGH level.
Reference: Standard digital electronics: open-collector outputs
Question 174
Digital ElectronicsProgrammable Logic Devices

In a conventional PROM, which part is programmed by the user?

  • AThe connections representing stored data
  • BThe number of address pins after fabrication
  • CThe semiconductor supply voltage
  • DThe clock frequency only
Report an error
Correct Answer: A. The connections representing stored data
Explanation: A PROM is manufactured with a fixed decoding structure and user-programmable storage connections, allowing a desired data pattern or truth table to be permanently programmed.
Reference: Standard digital electronics: PROM
Question 175
Digital ElectronicsDigital Interfaces

Multiple compatible open-collector outputs may share a properly pulled-up line to realize which useful connection, provided the logic convention is accounted for?

  • AWired logic
  • BAn analog integrator
  • CA flash ADC
  • DA ring oscillator only
Report an error
Correct Answer: A. Wired logic
Explanation: Because any active open-collector transistor can pull the common node LOW while inactive outputs release it, compatible outputs can share a pull-up line to implement wired logic.
Reference: Standard digital electronics: wired logic
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Question 176
Digital ElectronicsLogic Hazards

A static-0 hazard in a POS combinational circuit is an unwanted transition in which the output, ideally remaining 0, may briefly?

  • ARise to 1 and return to 0
  • BRemain permanently at 1
  • CEnter high impedance
  • DToggle only on a clock edge
Report an error
Correct Answer: A. Rise to 1 and return to 0
Explanation: A static-0 hazard is a temporary 0→1→0 glitch caused by unequal propagation delays when the correct steady output should remain LOW.
Reference: Standard digital electronics: static-0 hazards
Question 177
Digital ElectronicsLogic Hazards

A dynamic hazard is characterized by an output that should change once but instead?

  • AChanges multiple times before settling
  • BNever changes under any condition
  • CBecomes permanently high impedance
  • DAlways changes exactly once
Report an error
Correct Answer: A. Changes multiple times before settling
Explanation: A dynamic hazard occurs when unequal delays through multiple paths cause several output transitions before the circuit reaches its final correct value.
Reference: Standard digital electronics: dynamic hazards
Question 178
Digital ElectronicsArithmetic Circuits

For a 4-bit carry look-ahead group with bit propagate terms P0,P1,P2,P3, which product indicates that an input carry can propagate through all four bit positions?

  • AP0+P1+P2+P3
  • BP0P1P2P3
  • CP0⊕P1⊕P2⊕P3
  • DP0P3 only
Report an error
Correct Answer: B. P0P1P2P3
Explanation: A carry propagates through the entire group only if every bit position propagates it, so the group-propagate condition is the product P0P1P2P3.
Reference: Standard digital electronics: carry look-ahead group propagate
Question 179
Digital ElectronicsArithmetic Circuits

In unsigned binary subtraction A−B, a borrow is required at a bit position when the effective subtrahend at that position is?

  • AGreater than the available minuend bit after considering borrow-in
  • BAlways zero
  • CEqual to the minuend in every case
  • DIndependent of borrow-in
Report an error
Correct Answer: A. Greater than the available minuend bit after considering borrow-in
Explanation: A borrow is needed whenever the bit being subtracted, including any incoming borrow effect, exceeds the available minuend value at that position.
Reference: Standard digital electronics: binary subtraction
Question 180
Digital ElectronicsArithmetic Circuits

A 4-bit unsigned saturating adder is designed to clamp any result above its maximum representable value. What output should it produce when 1110₂ and 0101₂ are added?

  • A0011
  • B1111
  • C10011
  • D0000
Report an error
Correct Answer: B. 1111
Explanation: 14+5=19, which exceeds the 4-bit unsigned maximum of 15. A saturating adder clamps the result to 1111 rather than wrapping around.
Reference: Standard digital electronics: saturating arithmetic
Question 182
Digital ElectronicsData Path Circuits

Arithmetic right shift of a two’s-complement signed number differs from logical right shift because arithmetic right shift normally?

  • AReplicates the sign bit into the vacated MSB
  • BAlways inserts 0 into the MSB
  • CRotates the LSB into the MSB
  • DComplements every bit
Report an error
Correct Answer: A. Replicates the sign bit into the vacated MSB
Explanation: An arithmetic right shift preserves the sign of a two's-complement value by filling vacated most-significant positions with copies of the sign bit.
Reference: Standard digital electronics: arithmetic shift
Question 183
Digital ElectronicsData Path Circuits

Assuming no overflow and exact divisibility, an arithmetic right shift of a signed two’s-complement integer by one bit approximately corresponds to?

  • AMultiplication by 2
  • BDivision by 2
  • CAddition of 2
  • DBitwise complement
Report an error
Correct Answer: B. Division by 2
Explanation: A one-position arithmetic right shift moves each bit toward lower significance while preserving the sign, corresponding to signed division by 2 under the stated conditions.
Reference: Standard digital electronics: arithmetic shifts
Question 184
Digital ElectronicsCombinational Circuits

A magnitude comparator cascades several comparison blocks from least-significant to most-significant groups. Which information must be propagated between blocks to obtain the final comparison?

  • AA>B, A=B, and A<B conditions
  • BOnly parity
  • COnly clock frequency
  • DOnly carry-out from an adder
Report an error
Correct Answer: A. A>B, A=B, and A<B conditions
Explanation: Cascaded magnitude comparison requires greater-than, equal-to, and less-than status so higher-order groups can determine the overall relation correctly.
Reference: Standard digital electronics: cascaded magnitude comparators
Question 185
Digital ElectronicsEncoders & Decoders

A priority encoder has a VALID output in addition to encoded outputs. The VALID signal is useful primarily to indicate that?

  • AAt least one encoder input is asserted
  • BAll inputs are necessarily asserted
  • CThe output code is analog
  • DThe clock has stopped
Report an error
Correct Answer: A. At least one encoder input is asserted
Explanation: Without a valid indication, the encoded output corresponding to no active input can be ambiguous with the code for a legitimate input. VALID indicates that an asserted input exists.
Reference: Standard digital electronics: priority encoder valid output
Question 186
Digital ElectronicsEncoders & Decoders

A decoder with active-LOW outputs is enabled. What does selection of one output normally mean?

  • AThe selected output goes LOW while the others remain HIGH
  • BThe selected output goes HIGH while all others go LOW
  • CAll outputs become high impedance
  • DEvery output toggles continuously
Report an error
Correct Answer: A. The selected output goes LOW while the others remain HIGH
Explanation: For an active-LOW decoder, assertion is represented by logic 0, so the selected output is LOW and unselected outputs remain HIGH.
Reference: Standard digital electronics: active-low decoders
Question 187
Digital ElectronicsMultiplexers & Demultiplexers

In a multiplexer tree, two stages of 4-to-1 multiplexers can be arranged to select among how many data inputs when the second stage selects among four first-stage outputs?

  • A4
  • B8
  • C16
  • D32
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Correct Answer: C. 16
Explanation: Four first-stage 4-to-1 multiplexers select from 16 total inputs, and a second-stage 4-to-1 multiplexer selects one of their four outputs.
Reference: Standard digital electronics: multiplexer expansion
Question 188
Digital ElectronicsCounters

A counter is described as self-starting when, after entering an unused or invalid state, it?

  • AEventually returns to the intended counting sequence without external intervention
  • BStops permanently
  • CRequires power removal to recover
  • DAlways changes into an analog oscillator
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Correct Answer: A. Eventually returns to the intended counting sequence without external intervention
Explanation: A self-starting counter has next-state logic that directs unused states back into the valid sequence, preventing permanent lockout.
Reference: Standard digital electronics: self-starting counters
Question 189
Digital ElectronicsMemory

A dual-port memory is especially useful when a design requires?

  • ATwo independent access ports to the same memory array
  • BOnly one fixed address forever
  • CNo read operation
  • DAnalog voltage storage only
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Correct Answer: A. Two independent access ports to the same memory array
Explanation: Dual-port memory provides two access interfaces, enabling two agents or datapaths to access a shared memory array with suitable arbitration or port rules.
Reference: Standard digital electronics: dual-port memory
Question 190
Digital ElectronicsMemory

A FIFO memory is best described by which ordering rule?

  • AFirst data written is the first data read
  • BLast data written is always the first data read
  • CData is read in random analog order
  • DOnly zero values can be stored
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Correct Answer: A. First data written is the first data read
Explanation: FIFO means First-In, First-Out: entries leave the buffer in the same order in which they entered.
Reference: Standard digital electronics: FIFO
Question 191
Digital ElectronicsMemory

Which pair of pointer conditions is commonly used in a FIFO to determine whether reads or writes should be blocked?

  • AEmpty and full
  • BCarry and borrow only
  • CSet and reset only
  • DGain and phase
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Correct Answer: A. Empty and full
Explanation: FIFO control logic tracks read and write positions and derives EMPTY and FULL conditions to prevent invalid reads and overwriting of unread data.
Reference: Standard digital electronics: FIFO status
Question 192
Digital ElectronicsADC & DAC

A dual-slope ADC is particularly valued in digital measurement instruments because its integrating operation provides good rejection of?

  • ACertain periodic noise such as mains-frequency interference
  • BAll possible quantization error
  • CEvery clock error regardless of frequency
  • DMemory leakage
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Correct Answer: A. Certain periodic noise such as mains-frequency interference
Explanation: Dual-slope conversion integrates the input over a defined interval; choosing the interval appropriately can strongly reject periodic interference such as 50/60 Hz mains noise.
Reference: Standard digital electronics: dual-slope ADC
Question 193
Digital ElectronicsADC & DAC

In an ADC, differential nonlinearity (DNL) describes deviation of?

  • AAn individual code-bin width from the ideal 1-LSB step
  • BThe supply voltage from zero
  • CThe clock duty cycle from 100 percent
  • DThe number of output bits from an integer
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Correct Answer: A. An individual code-bin width from the ideal 1-LSB step
Explanation: DNL measures how much each actual transition step or code-bin width differs from the ideal one-LSB size.
Reference: Standard digital electronics: ADC differential nonlinearity
Question 194
Digital ElectronicsADC & DAC

An ADC is said to have a missing code when?

  • AAt least one digital output code is never produced for any input within the conversion range
  • BEvery code occurs twice
  • CThe input is exactly zero
  • DThe ADC has no clock pin
Report an error
Correct Answer: A. At least one digital output code is never produced for any input within the conversion range
Explanation: A missing code is an output value that the converter skips entirely as the analog input is swept through its range, often associated with excessive DNL.
Reference: Standard digital electronics: ADC missing codes
Question 195
Digital ElectronicsADC & DAC

For an ideal monotonic DAC, increasing the digital input code by one count should?

  • ANever cause the analog output to move in the opposite direction
  • BAlways force the output to zero
  • CReverse the output polarity every step
  • DProduce exactly two output transitions
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Correct Answer: A. Never cause the analog output to move in the opposite direction
Explanation: Monotonicity means the analog output never reverses direction when the input code changes monotonically in one direction.
Reference: Standard digital electronics: DAC monotonicity
Question 196
Digital ElectronicsADC & DAC

A DAC has a settling time specification of 2 microseconds. This specification primarily indicates the time required after an input-code change for the analog output to?

  • AEnter and remain within a specified error band around its final value
  • BBegin oscillating indefinitely
  • CBecome a digital code
  • DErase the input register
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Correct Answer: A. Enter and remain within a specified error band around its final value
Explanation: Settling time is measured from a code transition until the analog output reaches and stays within a specified tolerance around its final value.
Reference: Standard digital electronics: DAC settling time
Question 199
Digital ElectronicsFlip-Flops

A D flip-flop has D=Q̅ connected externally. Ignoring asynchronous controls, what behavior occurs on each active clock edge?

  • AIt toggles
  • BIt always resets
  • CIt always sets
  • DIt retains its state forever
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Correct Answer: A. It toggles
Explanation: Because the next D input is the complement of the current Q, each active edge loads the opposite state. The D flip-flop therefore behaves as a toggle element.
Reference: Standard digital electronics: D flip-flop feedback
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