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MAHATRANSCO MCQs

Practice MAHATRANSCO-oriented Electronics & Telecommunication Engineering MCQs with answers and explanations for technical exam preparation. Questions are arranged in pages of up to 100.

Question 1301
Digital ElectronicsSequential Timing

A positive-edge-triggered D flip-flop has setup time 3 ns and hold time 1 ns. For reliable operation, the D input must be stable for at least which interval around the active clock edge?

  • A3 ns before and 1 ns after
  • B1 ns before and 3 ns after
  • COnly 3 ns after
  • DOnly at the exact clock instant
Report an error
Correct Answer: A. 3 ns before and 1 ns after
Explanation: Setup time requires data to be stable for 3 ns before the active edge, and hold time requires it to remain stable for 1 ns after the edge.
Reference: Standard digital electronics: setup and hold time
Question 1302
Digital ElectronicsSequential Timing

If the setup or hold requirement of a flip-flop is violated, the flip-flop may temporarily enter which condition?

  • AMetastability
  • BPermanent tri-state
  • CFrequency lock
  • DQuantization
Report an error
Correct Answer: A. Metastability
Explanation: A timing violation can leave a bistable element temporarily between valid logic states. This metastable condition eventually resolves, but its resolution time is not precisely predictable.
Reference: Standard digital electronics: metastability
Question 1303
Digital ElectronicsClock Domain Crossing

Why is a two-flip-flop synchronizer commonly used when a single-bit asynchronous signal enters a synchronous clock domain?

  • ATo reduce the probability that metastability propagates into downstream logic
  • BTo double the asynchronous signal frequency
  • CTo convert binary to BCD
  • DTo remove the clock
Report an error
Correct Answer: A. To reduce the probability that metastability propagates into downstream logic
Explanation: The first flip-flop may become metastable, while the second provides additional resolution time before the signal is used by downstream synchronous logic, greatly reducing failure probability.
Reference: Standard digital electronics: asynchronous input synchronization
Question 1307
Digital ElectronicsCounters

A synchronous binary counter differs fundamentally from a ripple counter because in a synchronous counter?

  • AAll flip-flops are clocked by the common clock
  • BOnly the first flip-flop receives a clock
  • CEach stage is triggered only by the previous stage output
  • DNo flip-flops are used
Report an error
Correct Answer: A. All flip-flops are clocked by the common clock
Explanation: In a synchronous counter, all flip-flops receive the clock together and combinational logic determines which stages toggle. This avoids cumulative ripple clocking between stages.
Reference: Standard digital electronics: synchronous counters
Question 1309
Digital ElectronicsFlip-Flops

In an asynchronous clear input of a flip-flop, the term asynchronous means that clearing can occur?

  • AWithout waiting for an active clock edge
  • BOnly at the next clock edge
  • COnly when data input is HIGH
  • DOnly after two clock cycles
Report an error
Correct Answer: A. Without waiting for an active clock edge
Explanation: An asynchronous clear directly forces the stored state to the reset value independent of the normal clock transition.
Reference: Standard digital electronics: asynchronous reset
Question 1310
Digital ElectronicsShift Registers

A 16-bit shift register is clocked at 2 MHz. Ignoring loading overhead, how long does it take to shift 16 serial bits through 16 clock periods?

  • A1 microsecond
  • B4 microseconds
  • C8 microseconds
  • D16 microseconds
Report an error
Correct Answer: C. 8 microseconds
Explanation: At 2 MHz, one clock period is 0.5 microsecond. Sixteen clock periods therefore require 16 × 0.5 = 8 microseconds.
Reference: Standard digital electronics: serial shifting
Question 1313
Digital ElectronicsMemory

Compared with DRAM, a typical SRAM cell is generally?

  • AFaster and does not require periodic refresh
  • BSlower and always requires refresh
  • CNonvolatile without power
  • DImplemented with one storage capacitor only
Report an error
Correct Answer: A. Faster and does not require periodic refresh
Explanation: SRAM uses bistable circuitry and normally offers faster access without refresh, although it uses more devices per bit and has lower density than DRAM.
Reference: Standard digital electronics: SRAM versus DRAM
Question 1314
Digital ElectronicsMemory

Which nonvolatile memory can normally be electrically erased and rewritten at byte or small-unit granularity, unlike traditional UV-erasable EPROM?

  • AEEPROM
  • BSRAM
  • CDRAM
  • DRegister file only
Report an error
Correct Answer: A. EEPROM
Explanation: EEPROM is electrically erasable and programmable. Traditional EPROM requires ultraviolet light for erasure, while EEPROM supports electrical rewriting.
Reference: Standard digital electronics: EEPROM
Question 1315
Digital ElectronicsMemory

Flash memory differs from conventional byte-erasable EEPROM mainly because flash is commonly erased in?

  • ABlocks or sectors
  • BSingle transistor terminals only
  • CClock cycles only
  • DAnalog voltage levels only
Report an error
Correct Answer: A. Blocks or sectors
Explanation: Flash memory is generally organized so erase operations affect blocks or sectors, enabling higher density than conventional byte-oriented EEPROM implementations.
Reference: Standard digital electronics: flash memory
Question 1317
Digital ElectronicsADC & DAC

Ignoring overhead, an ideal 12-bit successive-approximation ADC that performs one bit decision per clock requires approximately how many comparison steps for one conversion?

  • A6
  • B10
  • C12
  • D4096
Report an error
Correct Answer: C. 12
Explanation: A SAR converter determines one output bit per successive approximation step, so an ideal 12-bit conversion requires about 12 bit decisions.
Reference: Standard digital electronics: SAR conversion
Question 1320
Digital ElectronicsADC & DAC

For an ideal R-2R ladder DAC, one major practical advantage over a binary-weighted-resistor DAC is that the ladder requires?

  • AOnly two resistor values
  • BNo resistors
  • CA different resistor for every possible code
  • DOnly capacitors
Report an error
Correct Answer: A. Only two resistor values
Explanation: An R-2R ladder is constructed using only R and 2R values, simplifying resistor matching and IC implementation compared with a wide range of binary-weighted resistor values.
Reference: Standard digital electronics: R-2R DAC
Question 1322
Digital ElectronicsADC & DAC

A sample-and-hold circuit placed ahead of an ADC is primarily used to?

  • AKeep the analog input approximately constant during conversion
  • BGenerate the ADC clock
  • CStore the final digital code permanently
  • DIncrease the number of ADC bits automatically
Report an error
Correct Answer: A. Keep the analog input approximately constant during conversion
Explanation: The sample-and-hold captures the instantaneous analog input and holds it nearly constant so the ADC sees a stable value while conversion is in progress.
Reference: Standard digital electronics: sample-and-hold
Question 1324
Digital ElectronicsNumber Systems & Codes

The Excess-3 code for decimal digit 6 is?

  • A0110
  • B1001
  • C1010
  • D1100
Report an error
Correct Answer: B. 1001
Explanation: Excess-3 represents a decimal digit by adding 3 and encoding the result in four-bit binary. For 6, 6+3=9, giving 1001.
Reference: Standard digital electronics: Excess-3 code
Question 1325
Digital ElectronicsNumber Systems & Codes

Which useful property does the Excess-3 decimal code possess?

  • AIt is self-complementing
  • BIt uses only three bits per decimal digit
  • CIt is a weighted 8421 code
  • DAdjacent values always differ by one bit
Report an error
Correct Answer: A. It is self-complementing
Explanation: Excess-3 is a self-complementing code: complementing all four bits of a digit code gives the Excess-3 code for the 9's complement of that decimal digit.
Reference: Standard digital electronics: Excess-3 properties
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Question 1326
Digital ElectronicsArithmetic Logic Units

A 4-bit ALU is designed to perform arithmetic and logic functions selected by control inputs. The term ALU stands for?

  • AArithmetic Logic Unit
  • BAsynchronous Latch Utility
  • CAnalog Level Unit
  • DAddress Logic Uplink
Report an error
Correct Answer: A. Arithmetic Logic Unit
Explanation: An Arithmetic Logic Unit is a combinational subsystem that performs selected arithmetic and logical operations on binary operands.
Reference: Standard digital electronics: ALU
Question 1327
Digital ElectronicsData Path Circuits

A barrel shifter differs from a simple serial shift register because a barrel shifter can typically?

  • AShift or rotate a word by multiple bit positions in one combinational operation
  • BStore data without any logic gates
  • CConvert analog voltage directly to binary
  • DRefresh DRAM rows
Report an error
Correct Answer: A. Shift or rotate a word by multiple bit positions in one combinational operation
Explanation: A barrel shifter uses combinational selection networks to shift or rotate an entire word by a selected number of positions without requiring one clock per bit position.
Reference: Standard digital electronics: barrel shifter
Question 1328
Digital ElectronicsDecoder Applications

To implement an arbitrary Boolean function of n input variables directly with a decoder and an OR gate, the decoder normally requires how many output minterm lines?

  • An
  • B2n
  • C2^n
  • Dn^2
Report an error
Correct Answer: C. 2^n
Explanation: An n-to-2^n decoder generates one output for each possible input minterm. The required minterm outputs can then be ORed to realize an SOP function.
Reference: Standard digital electronics: decoder realization of Boolean functions
Question 1330
Digital ElectronicsBCD Arithmetic

In 8421 BCD addition, if a 4-bit digit sum is greater than 1001₂ (decimal 9), which binary correction is added to obtain a valid BCD result?

  • A0011
  • B0110
  • C1001
  • D1010
Report an error
Correct Answer: B. 0110
Explanation: A BCD digit is valid only from 0000 through 1001. When the binary digit sum exceeds 9, adding 0110₂ corrects the result and generates the appropriate decimal carry.
Reference: Standard digital electronics: BCD addition
Question 1331
Digital ElectronicsLFSR & Sequence Generators

A maximal-length n-stage linear feedback shift register (LFSR), when configured with a primitive feedback polynomial and excluding the all-zero lock state, cycles through how many nonzero states?

  • An
  • B2n
  • C2^n - 1
  • D2^n
Report an error
Correct Answer: C. 2^n - 1
Explanation: A maximal-length LFSR generates a pseudorandom sequence containing every nonzero n-bit state once per period, giving 2^n−1 states.
Reference: Standard digital electronics: maximal-length LFSR
Question 1333
Digital ElectronicsLFSR & Sequence Generators

Why is the all-zero state normally excluded from an XOR-feedback LFSR sequence?

  • AIt can become a locked state that continues producing zeros
  • BIt causes the supply voltage to double
  • CIt automatically changes to all ones
  • DIt destroys the clock generator
Report an error
Correct Answer: A. It can become a locked state that continues producing zeros
Explanation: With XOR feedback, an all-zero register generally produces zero feedback, so every subsequent state remains all zero unless external logic forces the LFSR out of that state.
Reference: Standard digital electronics: LFSR lock state
Question 1334
Digital ElectronicsError Detection Codes

A cyclic redundancy check (CRC) treats a binary data sequence mathematically as?

  • AA polynomial over GF(2)
  • BA decimal floating-point number only
  • CAn analog waveform amplitude
  • DA Gray-code counter only
Report an error
Correct Answer: A. A polynomial over GF(2)
Explanation: CRC arithmetic represents bit strings as polynomials with binary coefficients and performs division using modulo-2 operations over GF(2).
Reference: Standard digital electronics: CRC
Question 1335
Digital ElectronicsError Detection Codes

In modulo-2 polynomial division used for CRC generation, subtraction is performed using?

  • AXOR without borrow
  • BOrdinary decimal subtraction with borrow
  • CXNOR with carry
  • DTwo's-complement multiplication
Report an error
Correct Answer: A. XOR without borrow
Explanation: Over GF(2), addition and subtraction are identical and correspond to XOR; there are no carries or borrows.
Reference: Standard digital electronics: CRC modulo-2 arithmetic
Question 1337
Digital ElectronicsDigital Interfaces

An open-collector logic output requires an external pull-up resistor mainly because the output stage can actively?

  • APull the line LOW but does not actively drive it HIGH
  • BDrive only HIGH and never LOW
  • CGenerate an analog sine wave
  • DStore a logic word
Report an error
Correct Answer: A. Pull the line LOW but does not actively drive it HIGH
Explanation: An open-collector output provides a transistor path to LOW when active. When inactive, the external pull-up resistor establishes the HIGH level.
Reference: Standard digital electronics: open-collector outputs
Question 1338
Digital ElectronicsProgrammable Logic Devices

In a conventional PROM, which part is programmed by the user?

  • AThe connections representing stored data
  • BThe number of address pins after fabrication
  • CThe semiconductor supply voltage
  • DThe clock frequency only
Report an error
Correct Answer: A. The connections representing stored data
Explanation: A PROM is manufactured with a fixed decoding structure and user-programmable storage connections, allowing a desired data pattern or truth table to be permanently programmed.
Reference: Standard digital electronics: PROM
Question 1339
Digital ElectronicsFPGA

A 4-input lookup table (LUT) in an FPGA can directly represent any Boolean function of up to four variables because it stores how many truth-table output bits?

  • A4
  • B8
  • C16
  • D32
Report an error
Correct Answer: C. 16
Explanation: Four binary inputs have 2^4=16 possible combinations. A 4-input LUT stores one output value for each combination, so 16 configuration bits represent an arbitrary four-variable Boolean function.
Reference: Standard digital electronics: FPGA LUT
Question 1340
Digital ElectronicsFPGA

In an FPGA, configurable logic blocks are interconnected primarily through?

  • AProgrammable routing resources
  • BFixed mechanical switches only
  • CAnalog transformers
  • DDRAM refresh lines only
Report an error
Correct Answer: A. Programmable routing resources
Explanation: FPGAs combine configurable logic resources with programmable interconnect, allowing the configured circuit's signal paths to be established after manufacture.
Reference: Standard digital electronics: FPGA architecture
Question 1341
Digital ElectronicsSequential Timing

For a register-to-register synchronous path, Tcq=2 ns, maximum combinational delay=11 ns, setup time=2 ns, and worst-case clock uncertainty=1 ns. What minimum clock period is required using Tclk ≥ Tcq + Tcomb + Tsetup + Tuncertainty?

  • A12 ns
  • B14 ns
  • C16 ns
  • D18 ns
Report an error
Correct Answer: C. 16 ns
Explanation: Substituting the values gives Tclk ≥ 2+11+2+1 = 16 ns.
Reference: Standard digital electronics: maximum clock frequency timing
Question 1343
Digital ElectronicsSequential Timing

A hold-time check in a synchronous register path is primarily concerned with which path characteristic?

  • AMinimum or contamination delay
  • BMaximum combinational delay only
  • CAverage propagation delay only
  • DPower-supply frequency
Report an error
Correct Answer: A. Minimum or contamination delay
Explanation: Hold analysis checks that new data cannot reach the destination flip-flop too soon after the active clock edge, so minimum path delay is critical.
Reference: Standard digital electronics: hold-time analysis
Question 1344
Digital ElectronicsFlip-Flops

Unlike an asynchronous reset, a synchronous reset normally changes a flip-flop’s state?

  • AOnly in association with the active clock edge
  • BImmediately regardless of the clock
  • COnly when power is removed
  • DOnly after the clock stops
Report an error
Correct Answer: A. Only in association with the active clock edge
Explanation: A synchronous reset is sampled as part of the clocked logic operation and therefore takes effect at the relevant active clock edge.
Reference: Standard digital electronics: synchronous reset
Question 1347
Digital ElectronicsDigital Interfaces

Multiple compatible open-collector outputs may share a properly pulled-up line to realize which useful connection, provided the logic convention is accounted for?

  • AWired logic
  • BAn analog integrator
  • CA flash ADC
  • DA ring oscillator only
Report an error
Correct Answer: A. Wired logic
Explanation: Because any active open-collector transistor can pull the common node LOW while inactive outputs release it, compatible outputs can share a pull-up line to implement wired logic.
Reference: Standard digital electronics: wired logic
Question 1348
Digital ElectronicsCombinational Circuits

A magnitude comparator cascades several comparison blocks from least-significant to most-significant groups. Which information must be propagated between blocks to obtain the final comparison?

  • AA>B, A=B, and A<B conditions
  • BOnly parity
  • COnly clock frequency
  • DOnly carry-out from an adder
Report an error
Correct Answer: A. A>B, A=B, and A<B conditions
Explanation: Cascaded magnitude comparison requires greater-than, equal-to, and less-than status so higher-order groups can determine the overall relation correctly.
Reference: Standard digital electronics: cascaded magnitude comparators
Question 1349
Digital ElectronicsEncoders & Decoders

A priority encoder has a VALID output in addition to encoded outputs. The VALID signal is useful primarily to indicate that?

  • AAt least one encoder input is asserted
  • BAll inputs are necessarily asserted
  • CThe output code is analog
  • DThe clock has stopped
Report an error
Correct Answer: A. At least one encoder input is asserted
Explanation: Without a valid indication, the encoded output corresponding to no active input can be ambiguous with the code for a legitimate input. VALID indicates that an asserted input exists.
Reference: Standard digital electronics: priority encoder valid output
Question 1350
Digital ElectronicsEncoders & Decoders

A decoder with active-LOW outputs is enabled. What does selection of one output normally mean?

  • AThe selected output goes LOW while the others remain HIGH
  • BThe selected output goes HIGH while all others go LOW
  • CAll outputs become high impedance
  • DEvery output toggles continuously
Report an error
Correct Answer: A. The selected output goes LOW while the others remain HIGH
Explanation: For an active-LOW decoder, assertion is represented by logic 0, so the selected output is LOW and unselected outputs remain HIGH.
Reference: Standard digital electronics: active-low decoders
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Question 1351
Digital ElectronicsMultiplexers & Demultiplexers

In a multiplexer tree, two stages of 4-to-1 multiplexers can be arranged to select among how many data inputs when the second stage selects among four first-stage outputs?

  • A4
  • B8
  • C16
  • D32
Report an error
Correct Answer: C. 16
Explanation: Four first-stage 4-to-1 multiplexers select from 16 total inputs, and a second-stage 4-to-1 multiplexer selects one of their four outputs.
Reference: Standard digital electronics: multiplexer expansion
Question 1352
Digital ElectronicsLogic Hazards

A static-0 hazard in a POS combinational circuit is an unwanted transition in which the output, ideally remaining 0, may briefly?

  • ARise to 1 and return to 0
  • BRemain permanently at 1
  • CEnter high impedance
  • DToggle only on a clock edge
Report an error
Correct Answer: A. Rise to 1 and return to 0
Explanation: A static-0 hazard is a temporary 0→1→0 glitch caused by unequal propagation delays when the correct steady output should remain LOW.
Reference: Standard digital electronics: static-0 hazards
Question 1353
Digital ElectronicsLogic Hazards

A dynamic hazard is characterized by an output that should change once but instead?

  • AChanges multiple times before settling
  • BNever changes under any condition
  • CBecomes permanently high impedance
  • DAlways changes exactly once
Report an error
Correct Answer: A. Changes multiple times before settling
Explanation: A dynamic hazard occurs when unequal delays through multiple paths cause several output transitions before the circuit reaches its final correct value.
Reference: Standard digital electronics: dynamic hazards
Question 1354
Digital ElectronicsArithmetic Circuits

For a 4-bit carry look-ahead group with bit propagate terms P0,P1,P2,P3, which product indicates that an input carry can propagate through all four bit positions?

  • AP0+P1+P2+P3
  • BP0P1P2P3
  • CP0⊕P1⊕P2⊕P3
  • DP0P3 only
Report an error
Correct Answer: B. P0P1P2P3
Explanation: A carry propagates through the entire group only if every bit position propagates it, so the group-propagate condition is the product P0P1P2P3.
Reference: Standard digital electronics: carry look-ahead group propagate
Question 1355
Digital ElectronicsArithmetic Circuits

In unsigned binary subtraction A−B, a borrow is required at a bit position when the effective subtrahend at that position is?

  • AGreater than the available minuend bit after considering borrow-in
  • BAlways zero
  • CEqual to the minuend in every case
  • DIndependent of borrow-in
Report an error
Correct Answer: A. Greater than the available minuend bit after considering borrow-in
Explanation: A borrow is needed whenever the bit being subtracted, including any incoming borrow effect, exceeds the available minuend value at that position.
Reference: Standard digital electronics: binary subtraction
Question 1356
Digital ElectronicsArithmetic Circuits

A 4-bit unsigned saturating adder is designed to clamp any result above its maximum representable value. What output should it produce when 1110₂ and 0101₂ are added?

  • A0011
  • B1111
  • C10011
  • D0000
Report an error
Correct Answer: B. 1111
Explanation: 14+5=19, which exceeds the 4-bit unsigned maximum of 15. A saturating adder clamps the result to 1111 rather than wrapping around.
Reference: Standard digital electronics: saturating arithmetic
Question 1358
Digital ElectronicsData Path Circuits

Arithmetic right shift of a two’s-complement signed number differs from logical right shift because arithmetic right shift normally?

  • AReplicates the sign bit into the vacated MSB
  • BAlways inserts 0 into the MSB
  • CRotates the LSB into the MSB
  • DComplements every bit
Report an error
Correct Answer: A. Replicates the sign bit into the vacated MSB
Explanation: An arithmetic right shift preserves the sign of a two's-complement value by filling vacated most-significant positions with copies of the sign bit.
Reference: Standard digital electronics: arithmetic shift
Question 1359
Digital ElectronicsData Path Circuits

Assuming no overflow and exact divisibility, an arithmetic right shift of a signed two’s-complement integer by one bit approximately corresponds to?

  • AMultiplication by 2
  • BDivision by 2
  • CAddition of 2
  • DBitwise complement
Report an error
Correct Answer: B. Division by 2
Explanation: A one-position arithmetic right shift moves each bit toward lower significance while preserving the sign, corresponding to signed division by 2 under the stated conditions.
Reference: Standard digital electronics: arithmetic shifts
Question 1360
Digital ElectronicsADC & DAC

A DAC has a settling time specification of 2 microseconds. This specification primarily indicates the time required after an input-code change for the analog output to?

  • AEnter and remain within a specified error band around its final value
  • BBegin oscillating indefinitely
  • CBecome a digital code
  • DErase the input register
Report an error
Correct Answer: A. Enter and remain within a specified error band around its final value
Explanation: Settling time is measured from a code transition until the analog output reaches and stays within a specified tolerance around its final value.
Reference: Standard digital electronics: DAC settling time
Question 1363
Digital ElectronicsFlip-Flops

A D flip-flop has D=Q̅ connected externally. Ignoring asynchronous controls, what behavior occurs on each active clock edge?

  • AIt toggles
  • BIt always resets
  • CIt always sets
  • DIt retains its state forever
Report an error
Correct Answer: A. It toggles
Explanation: Because the next D input is the complement of the current Q, each active edge loads the opposite state. The D flip-flop therefore behaves as a toggle element.
Reference: Standard digital electronics: D flip-flop feedback
Question 1365
Digital ElectronicsCounters

A counter is described as self-starting when, after entering an unused or invalid state, it?

  • AEventually returns to the intended counting sequence without external intervention
  • BStops permanently
  • CRequires power removal to recover
  • DAlways changes into an analog oscillator
Report an error
Correct Answer: A. Eventually returns to the intended counting sequence without external intervention
Explanation: A self-starting counter has next-state logic that directs unused states back into the valid sequence, preventing permanent lockout.
Reference: Standard digital electronics: self-starting counters
Question 1366
Digital ElectronicsMemory

A dual-port memory is especially useful when a design requires?

  • ATwo independent access ports to the same memory array
  • BOnly one fixed address forever
  • CNo read operation
  • DAnalog voltage storage only
Report an error
Correct Answer: A. Two independent access ports to the same memory array
Explanation: Dual-port memory provides two access interfaces, enabling two agents or datapaths to access a shared memory array with suitable arbitration or port rules.
Reference: Standard digital electronics: dual-port memory
Question 1367
Digital ElectronicsMemory

A FIFO memory is best described by which ordering rule?

  • AFirst data written is the first data read
  • BLast data written is always the first data read
  • CData is read in random analog order
  • DOnly zero values can be stored
Report an error
Correct Answer: A. First data written is the first data read
Explanation: FIFO means First-In, First-Out: entries leave the buffer in the same order in which they entered.
Reference: Standard digital electronics: FIFO
Question 1368
Digital ElectronicsMemory

Which pair of pointer conditions is commonly used in a FIFO to determine whether reads or writes should be blocked?

  • AEmpty and full
  • BCarry and borrow only
  • CSet and reset only
  • DGain and phase
Report an error
Correct Answer: A. Empty and full
Explanation: FIFO control logic tracks read and write positions and derives EMPTY and FULL conditions to prevent invalid reads and overwriting of unread data.
Reference: Standard digital electronics: FIFO status
Question 1369
Digital ElectronicsADC & DAC

A dual-slope ADC is particularly valued in digital measurement instruments because its integrating operation provides good rejection of?

  • ACertain periodic noise such as mains-frequency interference
  • BAll possible quantization error
  • CEvery clock error regardless of frequency
  • DMemory leakage
Report an error
Correct Answer: A. Certain periodic noise such as mains-frequency interference
Explanation: Dual-slope conversion integrates the input over a defined interval; choosing the interval appropriately can strongly reject periodic interference such as 50/60 Hz mains noise.
Reference: Standard digital electronics: dual-slope ADC
Question 1370
Digital ElectronicsADC & DAC

In an ADC, differential nonlinearity (DNL) describes deviation of?

  • AAn individual code-bin width from the ideal 1-LSB step
  • BThe supply voltage from zero
  • CThe clock duty cycle from 100 percent
  • DThe number of output bits from an integer
Report an error
Correct Answer: A. An individual code-bin width from the ideal 1-LSB step
Explanation: DNL measures how much each actual transition step or code-bin width differs from the ideal one-LSB size.
Reference: Standard digital electronics: ADC differential nonlinearity
Question 1371
Digital ElectronicsADC & DAC

An ADC is said to have a missing code when?

  • AAt least one digital output code is never produced for any input within the conversion range
  • BEvery code occurs twice
  • CThe input is exactly zero
  • DThe ADC has no clock pin
Report an error
Correct Answer: A. At least one digital output code is never produced for any input within the conversion range
Explanation: A missing code is an output value that the converter skips entirely as the analog input is swept through its range, often associated with excessive DNL.
Reference: Standard digital electronics: ADC missing codes
Question 1372
Digital ElectronicsADC & DAC

For an ideal monotonic DAC, increasing the digital input code by one count should?

  • ANever cause the analog output to move in the opposite direction
  • BAlways force the output to zero
  • CReverse the output polarity every step
  • DProduce exactly two output transitions
Report an error
Correct Answer: A. Never cause the analog output to move in the opposite direction
Explanation: Monotonicity means the analog output never reverses direction when the input code changes monotonically in one direction.
Reference: Standard digital electronics: DAC monotonicity
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Question 1377
Electronic Devices & CircuitsSemiconductor Fundamentals

Carrier drift current in a semiconductor is produced primarily by?

  • AAn applied electric field
  • BA carrier concentration gradient only
  • COptical reflection only
  • DA magnetic field with no electric field
Report an error
Correct Answer: A. An applied electric field
Explanation: Drift is the directed motion of charge carriers caused by an applied electric field.
Reference: Standard semiconductor electronics: drift current
Question 1378
Electronic Devices & CircuitsSemiconductor Fundamentals

Carrier diffusion current arises primarily because of?

  • AA spatial carrier-concentration gradient
  • BA perfectly uniform carrier concentration
  • CZero temperature only
  • DAn ideal short circuit
Report an error
Correct Answer: A. A spatial carrier-concentration gradient
Explanation: Diffusion results from random carrier motion combined with a concentration gradient, producing net transport from higher to lower concentration.
Reference: Standard semiconductor electronics: diffusion current
Question 1381
Electronic Devices & CircuitsPN Junction Diode

The small-signal resistance of a forward-biased diode at a fixed operating point is approximately proportional to?

  • AThermal voltage divided by diode current
  • BDiode current divided by thermal voltage
  • CSquare of reverse voltage only
  • DZero for every current
Report an error
Correct Answer: A. Thermal voltage divided by diode current
Explanation: From the exponential diode equation, the incremental resistance is approximately rd = nVT/ID at the operating point.
Reference: Standard semiconductor electronics: diode small-signal resistance
Question 1383
Electronic Devices & CircuitsPN Junction Diode

The junction capacitance of a reverse-biased PN diode generally does what as reverse-bias magnitude increases?

  • ADecreases
  • BIncreases without limit
  • CRemains exactly constant
  • DBecomes negative
Report an error
Correct Answer: A. Decreases
Explanation: Increasing reverse bias widens the depletion region. Since junction capacitance is inversely related to depletion width, the capacitance decreases.
Reference: Standard semiconductor electronics: transition capacitance
Question 1384
Electronic Devices & CircuitsSpecial Diodes

A varactor diode is primarily used as a voltage-controlled?

  • ACapacitance
  • BCurrent source
  • CInductance heater
  • DOptical amplifier
Report an error
Correct Answer: A. Capacitance
Explanation: A reverse-biased varactor exploits the voltage dependence of PN-junction capacitance, making it useful for electronic tuning.
Reference: Standard electronics: varactor diode
Question 1385
Electronic Devices & CircuitsPN Junction Diode

Avalanche breakdown in a PN junction is mainly associated with?

  • AImpact ionization and carrier multiplication
  • BForward-bias recombination only
  • CMechanical contact bounce
  • DZero electric field
Report an error
Correct Answer: A. Impact ionization and carrier multiplication
Explanation: In avalanche breakdown, carriers accelerated by a strong electric field create additional electron-hole pairs through impact ionization.
Reference: Standard semiconductor electronics: avalanche breakdown
Question 1386
Electronic Devices & CircuitsPN Junction Diode

Compared with avalanche breakdown, Zener breakdown is most strongly associated with?

  • AQuantum-mechanical tunneling in a heavily doped junction
  • BImpact ionization in a lightly doped junction only
  • CThermal radiation from an LED
  • DTransistor saturation
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Correct Answer: A. Quantum-mechanical tunneling in a heavily doped junction
Explanation: Zener breakdown occurs in heavily doped junctions with narrow depletion regions, where a strong field enables tunneling.
Reference: Standard semiconductor electronics: Zener breakdown mechanism
Question 1391
Electronic Devices & CircuitsBJT

The Early effect in a BJT refers primarily to variation of collector current with collector-emitter voltage due to?

  • ABase-width modulation
  • BGate-oxide tunneling
  • CZener regulation
  • DEmitter resistance only
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Correct Answer: A. Base-width modulation
Explanation: Increasing collector-base reverse bias widens the depletion region into the base, reducing effective base width and changing collector current; this is the Early effect.
Reference: Standard transistor electronics: Early effect
Question 1395
Electronic Devices & CircuitsFET & MOSFET

In a MOSFET, channel-length modulation in saturation causes the drain current to?

  • AIncrease slightly as VDS increases
  • BRemain exactly independent of VDS in every real device
  • CFall exactly to zero
  • DReverse direction automatically
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Correct Answer: A. Increase slightly as VDS increases
Explanation: Channel-length modulation shortens the effective channel as VDS rises, giving the saturation-region output characteristic a finite positive slope.
Reference: Standard electronics: MOSFET channel-length modulation
Question 1396
Electronic Devices & CircuitsFET & MOSFET

The body effect in an NMOS transistor generally causes threshold voltage magnitude to do what when source-to-body reverse bias increases?

  • AIncrease
  • BDecrease to zero
  • CRemain exactly unchanged
  • DBecome an AC frequency
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Correct Answer: A. Increase
Explanation: Increasing source-body reverse bias increases the threshold voltage required to form the inversion channel; this is the MOSFET body effect.
Reference: Standard electronics: MOSFET body effect
Question 1397
Electronic Devices & CircuitsAmplifier Frequency Response

A cascode amplifier is commonly used because it can provide high gain while reducing the influence of which high-frequency effect associated with input-output capacitance?

  • AMiller effect
  • BHall effect
  • CZener effect
  • DPhotoelectric effect
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Correct Answer: A. Miller effect
Explanation: The cascode keeps the voltage variation across the input transistor's feedback capacitance relatively small, reducing Miller multiplication and improving high-frequency response.
Reference: Standard analog electronics: cascode and Miller effect
Question 1398
Electronic Devices & CircuitsPN Junction Diode

A silicon PN junction has a reverse saturation current of 10 nA. Using the ideal diode equation with n=1 and VT=25 mV, approximately by what factor does the forward current increase when the forward voltage rises by 50 mV in the exponential region?

  • A2
  • B4
  • C7.4
  • D100
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Correct Answer: C. 7.4
Explanation: The current ratio is exp(ΔV/VT)=exp(50/25)=e^2≈7.4, assuming the exponential term dominates.
Reference: Standard semiconductor electronics: diode exponential characteristic
Question 1399
Electronic Devices & CircuitsPN Junction Diode

Reverse recovery time of a PN diode is mainly associated with?

  • ARemoval of stored charge when switching from forward conduction to reverse blocking
  • BTime required to heat the package
  • CForward voltage becoming exactly zero
  • DZener voltage regulation only
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Correct Answer: A. Removal of stored charge when switching from forward conduction to reverse blocking
Explanation: After forward conduction, stored minority-carrier charge must be removed before the diode fully blocks reverse current, producing reverse recovery time.
Reference: Standard semiconductor electronics: diode reverse recovery
Question 1400
Electronic Devices & CircuitsSpecial Diodes

A Schottky diode generally switches faster than an ordinary PN diode mainly because it is primarily a?

  • AMajority-carrier device with little minority-carrier charge storage
  • BDevice with an extremely thick depletion region only
  • CLight-emitting junction
  • DCurrent-controlled transistor
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Correct Answer: A. Majority-carrier device with little minority-carrier charge storage
Explanation: Schottky conduction mainly involves majority carriers, so there is little minority-carrier storage and reverse-recovery delay is small.
Reference: Standard electronics: Schottky diode
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