DRDO MCQs

Explanation: Carrier diffusion near the junction leaves uncovered fixed ionized donors and acceptors, forming the space-charge or depletion region.

Explanation: Forward bias opposes the built-in junction field, reducing the barrier potential and narrowing the depletion region.

Explanation: For basic circuit analysis, a forward-biased silicon PN diode is commonly approximated as having about a 0.7 V drop, although the actual value depends on current and temperature.

Explanation: A Zener diode is designed to operate safely in reverse breakdown, where its voltage remains approximately constant over a useful current range.

Explanation: Photodiodes are commonly reverse biased so incident light produces a measurable photocurrent with useful response speed and sensitivity.

Explanation: In an LED, injected electrons and holes recombine in the semiconductor and release energy as photons.

Explanation: The average value of one positive half-cycle over a complete cycle is Vm/pi, approximately 0.318Vm.

Explanation: Full-wave rectification makes both half-cycles positive, giving an average value of 2Vm/pi, approximately 0.637Vm.

Explanation: A full-wave rectifier produces two output pulses per input cycle, so its ripple frequency is twice the supply frequency: 100 Hz.

Explanation: In an intrinsic semiconductor, thermally generated electrons and holes occur in equal numbers, so n = p = ni.

Explanation: Pentavalent donor atoms contribute extra electrons, making electrons the majority carriers in an n-type semiconductor.

Explanation: Trivalent acceptor doping creates holes as the majority mobile carriers in p-type material.

Explanation: A FET is voltage controlled and normally draws very little gate current, giving it high input impedance.

Explanation: The JFET gate-channel PN junction is normally reverse biased, which keeps gate current very small and controls the channel depletion width.

Explanation: An enhancement-mode nMOS requires a positive gate-to-source voltage above threshold to induce a conducting channel; ideally it is off at VGS = 0.

Explanation: For an ideal inverting amplifier, Av = -Rf/Rin = -100 kOhm / 10 kOhm = -10.

Explanation: For a non-inverting amplifier, Av = 1 + Rf/R1 = 1 + 90/10 = 10.

Explanation: Because an ideal op-amp has infinite open-loop gain, linear negative-feedback operation forces its two input voltages to be approximately equal, often called a virtual short.

Explanation: The capacitor charges when the rectified voltage rises and supplies load current while the rectified input falls, smoothing the output voltage.

Explanation: The common-emitter current gain beta is defined approximately as IC/IB in the active region, hence IC = beta IB.

Explanation: IC = beta IB = 100 × 20 microampere = 2000 microampere = 2 mA.

Explanation: By current continuity in a BJT, the emitter current equals the sum of collector and base currents: IE = IC + IB.

Explanation: A common-emitter voltage amplifier is inverting, so its output voltage is approximately 180 degrees out of phase with its input.

Explanation: The common-emitter configuration provides both voltage and current gain and introduces phase inversion, making it widely used for amplification.

Explanation: In a common-collector stage, the output is taken from the emitter, which approximately follows the input voltage; hence the name emitter follower.

Explanation: For a silicon diode at a given forward current, the forward voltage typically decreases as junction temperature rises; a commonly used approximate coefficient is about -2 mV/°C near ordinary operating conditions.

Explanation: An ideal forward-biased diode has zero voltage drop and zero resistance, so it is represented as a short circuit.

Explanation: The theoretical maximum rectification efficiency of an ideal half-wave rectifier is approximately 40.6%.

Explanation: The theoretical maximum rectification efficiency of an ideal full-wave rectifier is approximately 81.2%.

Explanation: The standard ripple factor of an unfiltered ideal half-wave rectifier is approximately 1.21.

Explanation: The standard ripple factor of an unfiltered ideal full-wave rectifier is approximately 0.482, lower than that of a half-wave rectifier.

Explanation: In a center-tapped full-wave rectifier, the nonconducting diode can see approximately twice the peak voltage of one half-secondary, so PIV = 2Vm.

Explanation: In an ideal bridge rectifier, each reverse-biased diode must withstand approximately the peak secondary voltage Vm.

Explanation: Using alpha = IC/IE and beta = IC/IB with IE = IC + IB gives beta = alpha/(1-alpha).

Explanation: beta = alpha/(1-alpha) = 0.98/0.02 = 49.

Explanation: alpha = beta/(beta+1) = 99/100 = 0.99.

Explanation: beta = IC/IB = 4.95 mA / 0.05 mA = 99.

Explanation: The Q-point specifies the transistor's steady DC collector current and collector-emitter voltage with no input signal applied.

Explanation: Biasing near the center of the DC load line allows approximately equal signal swing toward cutoff and saturation.

Explanation: An emitter resistor develops degenerative negative feedback, helping stabilize the operating point and improving linearity, though it reduces gain.

Explanation: The common-base current gain is alpha = IC/IE, normally close to but less than 1.

Explanation: A common-collector or emitter-follower stage has a non-inverting voltage gain slightly less than unity in practice and approximately +1 ideally.

Explanation: Substituting VGS = 0 gives ID = IDSS(1 - 0)^2 = IDSS.

Explanation: The threshold voltage VTH is the gate-source voltage at which a conducting inversion channel begins to form according to the device model.

Explanation: The MOS gate is insulated from the channel by an oxide layer, so ideal steady-state gate current is zero, giving very high input resistance.

Explanation: The ideal op-amp model assumes infinite open-loop voltage gain.

Explanation: The ideal op-amp draws no input current, implying infinite input resistance, and acts as an ideal voltage source at its output, implying zero output resistance.

Explanation: For equal input and feedback resistors, Vo = -(V1 + V2) = -(1 + 2) = -3 V.

Explanation: An ideal inverting integrator produces Vo = -(1/RC) integral(Vin dt), within its intended operating range.

Explanation: For the ideal inverting differentiator, Vo = -RC(dVin/dt), so output is proportional to the input's time derivative with inversion.

Explanation: For a BJT, gm = IC/VT. Thus gm = 1 mA / 25 mV = 0.04 S = 40 mS.

Explanation: In the hybrid-pi model, r_pi = beta/gm = 100/0.04 = 2500 ohm = 2.5 kOhm.

Explanation: For a dominant-pole compensated op-amp, closed-loop gain multiplied by bandwidth is approximately constant over the usual operating range.

Explanation: At signal frequencies where the capacitor effectively bypasses the emitter resistor, emitter degeneration is reduced, so the voltage-gain magnitude generally increases.

Explanation: For a single-pole op-amp, bandwidth ≈ GBW/closed-loop gain = 1 MHz/10 = 100 kHz.

Explanation: A negative voltage gain indicates that the output voltage is inverted relative to the input, corresponding to approximately 180 degrees phase difference.

Explanation: With no linear negative feedback, an ideal comparator drives its output toward positive saturation when the non-inverting input exceeds the inverting input.

Explanation: Voltage gain magnitude = 2 V / 0.020 V = 100.

Explanation: Hysteresis provides different thresholds for rising and falling inputs, reducing unwanted switching caused by noise near a single threshold.

Explanation: Voltage gain in dB is 20 log10(Av). For Av = 100, 20 log10(100) = 40 dB.

Explanation: JFET transconductance is gm = dID/dVGS at the operating point, describing how effectively gate voltage controls drain current.

Explanation: Negative feedback normally reduces closed-loop gain but improves stability, linearity and bandwidth.

Explanation: ID = IDSS(1 - VGS/VP)^2 = 8(1 - (-2/-4))^2 = 8(0.5)^2 = 2 mA.

Explanation: A_f = 1000/(1 + 1000×0.09) = 1000/91 ≈ 10.99, approximately 11.

Explanation: In the long-channel ideal saturation model, ID is proportional to the square of the overdrive voltage VGS - VTH, neglecting channel-length modulation.

Explanation: At the oscillation frequency, the loop must provide positive regenerative feedback: |A beta| ≈ 1 and total loop phase shift 0 degrees modulo 360 degrees.

Explanation: For the standard long-channel model, the device is on when VGS > VTH and enters saturation when VDS is at least the overdrive voltage VGS - VTH.

Explanation: The inverting amplifier contributes about 180 degrees, while the RC network contributes another 180 degrees so the total loop phase shift is 360 degrees.

Explanation: The Wien-bridge oscillator is a common audio/low-frequency sine-wave oscillator capable of low distortion with suitable amplitude stabilization.

Explanation: The resonance frequency of an ideal LC circuit is f0 = 1/(2π√(LC)).

Explanation: f0 = 1/(2π√(10^-3 × 10^-6)) ≈ 1591.5 Hz, or about 1.59 kHz.

Explanation: Common-mode rejection ratio compares differential gain with common-mode gain; a high CMRR indicates strong rejection of signals common to both inputs.

Explanation: CMRR = Ad/Acm = 100000. In dB, 20 log10(100000) = 100 dB.

Explanation: Slew rate is the maximum large-signal rate at which the op-amp output voltage can change, commonly expressed in V/microsecond.

Explanation: Time = voltage change / slew rate = 10 V / (0.5 V/microsecond) = 20 microseconds.

Explanation: IB = (VCC - VBE)/RB = 9.3 V / 470 kOhm ≈ 19.8 microampere, about 20 microampere.

Explanation: IC = beta IB = 100 × 20 microampere = 2 mA.

Explanation: Temperature-dependent increases in leakage/current can raise power dissipation, causing additional heating and potentially a regenerative failure process if bias is not stabilized.

Explanation: Voltage-divider bias combined with emitter feedback makes the operating point less dependent on transistor beta than simple fixed-base bias.

Explanation: For a conventional series-fed resistive class-A power amplifier, the maximum theoretical collector efficiency is 25%. Transformer-coupled class-A operation can ideally reach 50%.

Explanation: Using rd ≈ VT/ID gives 25 mV / 1 mA = 25 ohm.

Explanation: The resistor sees approximately 5 - 0.7 = 4.3 V, so I = 4.3 V / 1 kOhm = 4.3 mA.

Explanation: IZ = (12 - 5.1)/690 = 6.9/690 = 0.01 A = 10 mA.

Explanation: In a biased clipper, conduction begins when the input reaches a level set by the DC bias plus or minus the diode forward drop, depending on circuit orientation.

Explanation: A clamper shifts a waveform vertically by adding a DC component while ideally retaining the waveform shape and peak-to-peak amplitude.

Explanation: A larger load resistance reduces load current and slows capacitor discharge between charging peaks, thereby reducing ripple.

Explanation: A larger capacitance stores more charge and its voltage falls less between rectified peaks, reducing ripple.

Explanation: The drop across RC is IC RC = 2 mA × 2 kOhm = 4 V. Thus VCE ≈ 10 - 4 = 6 V.

Explanation: 80 dB means Ad/Acm = 10^(80/20) = 10000. Therefore Acm = 100000/10000 = 10.

Explanation: The ideal maximum efficiency of a class-B push-pull amplifier is pi/4, or approximately 78.5%.

Explanation: Near zero crossing, neither transistor may conduct until the input exceeds the required base-emitter threshold, producing a dead zone and crossover distortion.

Explanation: Class-AB biases the output devices slightly on around zero crossing, substantially reducing crossover distortion while retaining better efficiency than class A.

Explanation: Like the BJT common-emitter stage, the common-source FET voltage amplifier is inverting and produces approximately 180 degrees phase reversal.

Explanation: The common-drain FET stage, called a source follower, has behavior analogous to the BJT common-collector or emitter-follower stage.

Explanation: MOSFET overdrive voltage is VOV = VGS - VTH = 5 - 2 = 3 V.

Explanation: The ideal saturation boundary is VDS >= VGS - VTH. Here the overdrive voltage is 3 V, so VDS must be at least about 3 V.

Explanation: For matched ratios, Vo = (R2/R1)(V2 - V1) = 10(0.3 - 0.1) = 2 V.

Explanation: Av = -Rf/Rin = -10, so Vo = -10 × 0.25 V = -2.5 V, assuming the output remains within the supply limits.

Explanation: For a non-inverting amplifier, Av = 1 + Rf/R1. Thus 6 = 1 + Rf/10 kOhm, giving Rf = 50 kOhm.

Explanation: fmax = SR/(2πVp) = 10^6 V/s /(2π×10 V) ≈ 15.9 kHz.